gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-07	mem: Fix a bug in the memory serialization file naming	Andreas Hansson
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-10-15	Mem: Separate the host and guest views of memory backing store	Andreas Hansson
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-25	Mem: Add simple bandwidth stats to PhysicalMemory	Ali Saidi
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2011-12-01	physmem: Improved fatal message for size mismatch	Brad Beckmann
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-06-08	Mem: Use sysconf to get the page size instead of the PAGE_SIZE macro.	Gabe Black
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-01	Spelling: Fix the a spelling error by changing mmaped to mmapped.	Gabe Black
2011-02-23	Mem: Print out memory when access > 8 bytes	Ali Saidi
2011-02-23	Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...	Ali Saidi
2010-11-19	SE: Fix simulating more than 4GB of RAM in SE mode	Ali Saidi
2010-11-08	ARM: Add checkpointing support	Ali Saidi
2010-11-08	Mem: Finish half-baked support for mmaping file in physmem.	Ali Saidi
2010-01-19	util: do checkpoint aggregation more cleanly, fix last changeset.	Lisa Hsu
2009-11-04	build: fix compile problems pointed out by gcc 4.4	Nathan Binkert
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-06-15	physmem: Add a null option to physical memory so it doesn't store data.	Nathan Binkert
2008-04-10	PhysicalMemory: Add parameter for variance in memory delay.	Ali Saidi
2008-01-02	Additional comments and helper functions for PrintReq.	Steve Reinhardt
2008-01-02	Add functional PrintReq command for memory-system debugging.	Steve Reinhardt
2007-11-19	Memory: Cache the physical memory start and size so we don't need a dynamic c...	Ali Saidi
2007-11-14	remove unnecessary debug messages I added	Korey Sewell
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-07-29	memory system: fix functional access bug.	Steve Reinhardt
2007-07-26	Merge python and x86 changes with cache branch	Nathan Binkert
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt
2007-05-28	Restructure SimpleTimingPort a bit:	Steve Reinhardt