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path: root/src/mem/physical.cc
AgeCommit message (Expand)Author
2011-02-23Mem: Print out memory when access > 8 bytesAli Saidi
2011-02-23Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...Ali Saidi
2010-11-19SE: Fix simulating more than 4GB of RAM in SE modeAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08Mem: Finish half-baked support for mmaping file in physmem.Ali Saidi
2010-01-19util: do checkpoint aggregation more cleanly, fix last changeset.Lisa Hsu
2009-11-04build: fix compile problems pointed out by gcc 4.4Nathan Binkert
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-06-15physmem: Add a null option to physical memory so it doesn't store data.Nathan Binkert
2008-04-10PhysicalMemory: Add parameter for variance in memory delay.Ali Saidi
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2007-11-19Memory: Cache the physical memory start and size so we don't need a dynamic c...Ali Saidi
2007-11-14remove unnecessary debug messages I addedKorey Sewell
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-07-29memory system: fix functional access bug.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-05-28Restructure SimpleTimingPort a bit:Steve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-02-12some forgotten commitsAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-01-26make our code a little more standards compliantAli Saidi
2006-12-27Change MemoryAccess dprintfs to print the data as wellAli Saidi
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ...Gabe Black
2006-11-20Fix an assert to correctly make sure a request falls entirely inside a memory.Gabe Black
2006-11-12Physical memory overrides the tport version of recvFunctional, need to do theRon Dreslinski
2006-11-09Get SPARC to the point that it starts running. Add ability to load the ROM bi...Ali Saidi
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
2006-10-12Fix problems with unCacheable addresses in timing-coherenceRon Dreslinski
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-09Make memtest work with 8 memtestersRon Dreslinski
2006-10-09Update memory assertion to check for whole range.Kevin Lim
2006-10-08Only respond if the pkt needs a response.Ron Dreslinski
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt