| Age | Commit message (Expand) | Author |
|---|
| 2016-08-22 | cpu, mem, sim: Change how KVM maps memory | David Hashe |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-02-16 | mem: mmap the backing store with MAP_NORESERVE | Andreas Hansson |
| 2015-02-16 | mem: Use the range cache for lookup as well as access | Andreas Hansson |
| 2014-10-16 | mem: Modernise PhysicalMemory with C++11 features | Andreas Hansson |
| 2013-01-07 | mem: Merge ranges that are part of the conf table | Andreas Hansson |
| 2012-10-15 | Mem: Separate the host and guest views of memory backing store | Andreas Hansson |
| 2012-09-19 | AddrRange: Transition from Range<T> to AddrRange | Andreas Hansson |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
| 2012-03-30 | Ruby: Remove the physMemPort and instead access memory directly | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-01-25 | Mem: Add simple bandwidth stats to PhysicalMemory | Ali Saidi |
| 2012-01-17 | MEM: Separate queries for snooping and address ranges | Andreas Hansson |
| 2010-11-19 | SE: Fix simulating more than 4GB of RAM in SE mode | Ali Saidi |
| 2010-11-08 | ARM: Add checkpointing support | Ali Saidi |
| 2010-11-08 | Mem: Finish half-baked support for mmaping file in physmem. | Ali Saidi |
| 2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert |
| 2009-04-21 | Minor tweaks for future Ruby compatibility. | Steve Reinhardt |
| 2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
| 2008-09-10 | style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul... | Ali Saidi |
| 2008-04-10 | PhysicalMemory: Add parameter for variance in memory delay. | Ali Saidi |
| 2007-11-19 | Memory: Cache the physical memory start and size so we don't need a dynamic c... | Ali Saidi |
| 2007-07-26 | Merge python and x86 changes with cache branch | Nathan Binkert |
| 2007-07-23 | Major changes to how SimObjects are created and initialized. Almost all | Nathan Binkert |
| 2007-06-17 | More major reorg of cache. Seems to work for atomic mode now, | Steve Reinhardt |
| 2007-05-21 | Change getDeviceAddressRanges to use bool for snoop arg. | Steve Reinhardt |
| 2007-05-19 | PhysicalMemory has vector of uniform ports instead of one special one. | Steve Reinhardt |
| 2007-02-12 | rename store conditional stuff as extra data so it can be used for conditiona... | Ali Saidi |
| 2006-11-22 | Added a parameter to set memory to zero. This is to support Legion, and once ... | Gabe Black |
| 2006-10-20 | Use PacketPtr everywhere | Nathan Binkert |
| 2006-10-08 | Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) | Steve Reinhardt |
| 2006-08-30 | Move more common functionality into SimpleTimingPort, | Steve Reinhardt |
| 2006-08-16 | DRAM Memory doesn't crash the simulator now.. still untested. | Ali Saidi |
| 2006-08-16 | Fix Physical Memory to allow memory sizes bigger than 128MB. | Ali Saidi |
| 2006-07-20 | Move PioPort timing code into Simple Timing Port object | Ali Saidi |
| 2006-06-13 | Move SimObject creation and Port connection loops | Steve Reinhardt |
| 2006-05-31 | Updated Authors from bk prs info | Ali Saidi |
| 2006-05-26 | Add names to memory Port objects for tracing. | Steve Reinhardt |
| 2006-05-22 | New directory structure: | Steve Reinhardt |
