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path: root/src/mem/physical.hh
AgeCommit message (Expand)Author
2009-04-21Minor tweaks for future Ruby compatibility.Steve Reinhardt
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-04-10PhysicalMemory: Add parameter for variance in memory delay.Ali Saidi
2007-11-19Memory: Cache the physical memory start and size so we don't need a dynamic c...Ali Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2006-11-22Added a parameter to set memory to zero. This is to support Legion, and once ...Gabe Black
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt
2006-08-30Move more common functionality into SimpleTimingPort,Steve Reinhardt
2006-08-16DRAM Memory doesn't crash the simulator now.. still untested.Ali Saidi
2006-08-16Fix Physical Memory to allow memory sizes bigger than 128MB.Ali Saidi
2006-07-20Move PioPort timing code into Simple Timing Port objectAli Saidi
2006-06-13Move SimObject creation and Port connection loopsSteve Reinhardt
2006-05-31Updated Authors from bk prs infoAli Saidi
2006-05-26Add names to memory Port objects for tracing.Steve Reinhardt
2006-05-22New directory structure:Steve Reinhardt