gem5 - gem5

Age	Commit message (Collapse)	Author
2013-02-10	ruby: replaces Time with Cycles in many places	Nilay Vaish
	The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
2012-09-30	MI coherence protocol: add copyright notice	Nilay Vaish

2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
	This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
2011-06-08	Ruby: Correctly set access permissions for directory entries	Nilay Vaish
	The access permissions for the directory entries are not being set correctly. This is because pointers are not used for handling directory entries. function. get and set functions for access permissions have been added to the Controller state machine. The changePermission() function provided by the AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC code once again. The set_permission() functionality has been removed. NOTE: Each protocol will have to define these get and set functions in order to compile successfully.
2011-05-20	slicc: added vnet_type to MI_example	Tushar Krishna
	Forgot to add this to MI_example in my previous patch.
2011-02-23	ruby: automate permission setting	Brad Beckmann
	This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2010-03-21	ruby: Reordered protocol buffers	Brad Beckmann
	Reordered vnet priorities to agree with PerfectSwitch for protocols MI_example, MOESI_CMP_token, and MOESI_hammer
2010-03-21	ruby: Minor dma latency initialization fix	Brad Beckmann

2010-01-29	ruby: MI_example updates to use the new config system	Brad Beckmann

2009-11-18	ruby: Removed unused action z_stall	Brad Beckmann

2009-11-18	ruby: fixed dma mi example to work with multiple dma ports	Brad Beckmann

2009-08-04	slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers	Derek Hower
	This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported.
2009-07-18	ruby: fixed dma sequencer bug	Derek Hower
	The DMASequencer was still using a parameter from the old RubyConfig, causing an offset error when the requested data wasn't block aligned. This changeset also includes a fix to MI_example for a similar bug.
2009-07-06	ruby: Import the latest ruby changes from gems.	Nathan Binkert
	This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.