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path: root/src/mem/protocol/RubySlicc_ComponentMapping.sm
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2011-10-28Ruby: Reorganize mapping of componentsNilay Vaish
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for mapping MachineType to GenericMachineType. These '#define's are being eliminated and the code will now be generated by SLICC instead. Also are being eliminated some of the unused functions from RubySlicc_ComponentMapping.sm.
2010-01-29ruby: removed last level cache supportBrad Beckmann
Removed the last level cache support and MOESI_hammer's dependency on it. Replaces the LLC support with the more generic MachineType count.
2010-01-19mergeDerek Hower
2009-11-18ruby: returns the number of LLC needed for broadcastBrad Beckmann
Added feature to CacheMemory to return the number of last level caches. This count is need for broadcast protocols such as MOESI_hammer.
2009-09-15ruby: added broadcast mechanismDerek Hower
2009-08-04slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllersDerek Hower
This changeset contains a lot of different changes that are too mingled to separate. They are: 1. Added MOESI_CMP_directory I made the changes necessary to bring back MOESI_CMP_directory, including adding a DMA controller. I got rid of MOESI_CMP_directory_m and made MOESI_CMP_directory use a memory controller. Added a new configuration for two level protocols in general, and MOESI_CMP_directory in particular. 2. DMA Sequencer uses a generic SequencerMsg I will eventually make the cache Sequencer use this type as well. It doesn't contain an offset field, just a physical address and a length. MI_example has been updated to deal with this. 3. Parameterized Controllers SLICC controllers can now take custom parameters to use for mapping, latencies, etc. Currently, only int parameters are supported.
2009-07-06ruby: Import the latest ruby changes from gems.Nathan Binkert
This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.
2009-05-11ruby: Import ruby and slicc from GEMSNathan Binkert
We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother.