gem5 - gem5

Age	Commit message (Expand)	Author
2019-05-14	mem-ruby: Unique ranks for MOESI_CMP_dir in ports	Tiago Muck
2019-05-14	mem-ruby: Change MOESI_CMP_Dir L2 addressing	Tiago Muck
2019-05-14	mem-ruby: Fix MOESI_CMP_dir debug msg	Tiago Muck
2019-05-14	mem-ruby: Prevent response stalls on MOESI_CMP_directory	Tiago Muck
2019-05-09	mem-ruby: Fix MOESI_CMP_directory blocked line handling	Tiago Muck
2019-02-12	mem-ruby: Fixing MESI Three Level	Pouya Fotouhi
2019-01-23	mem-ruby: Fix missing TBE allocation and deallocation	Zicong Wang
2018-10-26	mem-ruby: Fix MOESI_CMP_directory in ports order	Nikos Nikoleris
2018-04-13	ruby,gpu-compute: bugfix for GPU_VIPER* protocols	Brandon Potter
2018-04-13	ruby: bugfix for MESI_Three_Level protocol	Brandon Potter
2018-04-13	mem-ruby: fix more style issues in AMD licenses	Tony Gutierrez
2018-04-12	configs, mem-ruby: fix issues with style in AMD license	Tony Gutierrez
2018-03-12	mem-ruby: Fix RubyPrefetcher support in MESI_Two_Level	Rico Amslinger
2018-01-11	mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol	Nikos Nikoleris
2018-01-11	mem-ruby: Remove function that maps responses to a DMA engine	Nikos Nikoleris
2018-01-11	mem-ruby: Add support for multiple DMA engines in MESI_Two_Level	Nikos Nikoleris
2017-11-10	scons: Move Transform and termcap functionality into their own files.	Gabe Black
2017-06-13	ruby: Add support for address ranges in the directory	Nikos Nikoleris
2017-04-05	ruby: Fix MOESI_CMP_directory for new DMA status changes.	Javier Cano-Cano
2016-11-19	ruby: init MessageSizeType of SequencerMsg to Request_Control	Sooraj Puthoor
2016-10-26	ruby: Allow multiple outstanding DMA requests	Michael LeBeane
2016-10-06	ruby: rename ALPHA_Network_test protocol to Garnet_standalone.	Tushar Krishna
2016-04-26	ruby: Rename pkt to m_pkt so it may be accessed via SLICC	Matthew Poremba
2016-01-22	ruby: removed Write_Only AccessPermission	Brad Beckmann
2016-01-19	gpu-compute: AMD's baseline GPU model	Tony Gutierrez
2016-01-19	mem: write combining for ruby protocols	Tony Gutierrez
2016-01-19	* * *	Tony Gutierrez
2015-07-20	mem: misc flags for AMD gpu model	Blake Hechtman
2015-07-20	ruby: slicc: have a static MachineType	Tony Gutierrez
2015-07-20	ruby: slicc: remove support for single machine, multiple types	Tony Gutierrez
2015-11-13	slicc: fixes for the Address to Addr changeset (11025)	Tony Gutierrez
2015-11-13	ruby: add BoolVec	Joe Gross
2015-09-23	ruby: bloom filters: refactor code	Nilay Vaish
2015-09-18	ruby: print addresses in hex	Nilay Vaish
2015-09-16	ruby: Add missing block deallocations in MOESI_hammer	Lena Olson
2015-09-16	ruby: message buffer, timer table: significant changes	Nilay Vaish
2015-09-16	slicc: export uint64_t instead of uint64	Anthony Gutierrez
2015-09-05	ruby: call setMRU from L1 controllers, not from sequencer	Nilay Vaish
2015-09-05	ruby: declare all protocol message buffers as parameters	Nilay Vaish
2015-08-19	ruby: reverts to changeset: bf82f1f7b040	Nilay Vaish
2015-08-14	ruby: add accessor functions to SLICC def of MachineID	Nilay Vaish
2015-08-14	ruby: call setMRU from L1 controllers, not from sequencer	Nilay Vaish
2015-08-14	ruby: drop the [] notation for lookup function.	Nilay Vaish
2015-08-14	ruby: replace Address by Addr	Nilay Vaish
2015-08-14	ruby: rename variables Addr to addr	Nilay Vaish
2015-08-14	ruby: Protocol changes for SimObject MessageBuffers	Joel Hestness
2015-08-14	ruby: Expose MessageBuffers as SimObjects	Joel Hestness
2015-08-14	ruby: Change PerfectCacheMemory::lookup to return pointer	Joel Hestness
2015-08-03	ruby: mesi three level: multiple corrections to the protocol	Nilay Vaish
2015-08-03	ruby: mesi two,three level: copy data only when dirty	Nilay Vaish