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2014-05-23ruby: remove old protocol documentationNilay Vaish
2014-05-23ruby: message buffer: drop dequeue_getDelayCycles()Nilay Vaish
The functionality of updating and returning the delay cycles would now be performed by the dequeue() function itself.
2014-04-08ruby: slicc: change enqueue statementNilay Vaish
As of now, the enqueue statement can take in any number of 'pairs' as argument. But we only use the pair in which latency is the key. This latency is allowed to be either a fixed integer or a member variable of controller in which the expression appears. This patch drops the use of pairs in an enqueue statement. Instead, an expression is allowed which will be interpreted to be the latency of the enqueue. This expression can anything allowed by slicc including a constant integer or a member variable.
2014-04-08ruby: coherence protocols: drop the phrase IntraChipNilay Vaish
The phrase is no longer valid since we do not distinguish between inter and intra chip communication.
2014-02-23ruby: protocols: remove unused action z_stallNilay Vaish
2014-02-20ruby: mesi three level: rename incorrectly named filesNilay Vaish
Two files had been incorrectly named with a .cache suffix. --HG-- rename : src/mem/protocol/MESI_Three_Level-L0.cache => src/mem/protocol/MESI_Three_Level-L0cache.sm rename : src/mem/protocol/MESI_Three_Level-L1.cache => src/mem/protocol/MESI_Three_Level-L1cache.sm
2014-01-17ruby: remove unused label no_vectorNilay Vaish
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers.
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
This is because the next patch introduces a three level hierarchy. --HG-- rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
2014-01-04ruby: add support for clustersNilay Vaish
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
2013-12-26ruby: fix bugs in mesi cmp directory protocolNilay Vaish
This patch fixes couple of bugs in the L2 controller of the mesi cmp directory protocol. 1. The state MT_I was transitioning to NP on receiving a clean writeback from the L1 controller. This patch makes it inform the directory controller about the writeback. 2. The L2 controller was sending the dirty bit to the L1 controller and the L2 controller used writeback from the L1 controller to update the dirty bit unconditionally. Now, the L1 controller always assumes that the incoming data is clean. The L2 controller updates the dirty bit only when the L1 controller writes to the block. 3. Certain unused functions and events are being removed.
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
The directory controller should not have the sharer field since there is only one level 2 cache. Anyway the field was not in use. The owner field was being used to track the l2 cache version (in case of distributed l2) that has the cache block under consideration. The information is not required since the version of the level 2 cache can be obtained from a subset of the address bits.
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
This patch adds missing initializations of the SenderMachine field of out_msg's when thery are created in the L2 cache controller of the MOESI_CMP_directory coherence protocol. When an out_msg is created and this field is left uninitialized, it is set to the default value MachineType_NUM. This causes a panic in the MachineType_to_string function when gem5 is executed with the Ruby debug flag on and it tries to print the message. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-09-06ruby: remove undefined message size typeNilay Vaish
This message size type does not work well with one of the statistical variables. It also seems unnecessary.
2013-06-25ruby: moesi cmp directory: separate actions for external hitsNilay Vaish
This patch adds separate actions for requests that missed in the local cache and messages were sent out to get the requested line. These separate actions are required for differentiating between the hit and miss latencies in the statistics collected.
2013-06-25ruby: mesi cmp directory: separate actions for external hitsNilay Vaish
This patch adds separate actions for requests that missed in the local cache and messages were sent out to get the requested line. These separate actions are required for differentiating between the hit and miss latencies in the statistics collected.
2013-06-25ruby: profiler: lots of inter-related changesNilay Vaish
The patch started of with removing the global variables from the profiler for profiling the miss latency of requests made to the cache. The corrresponding histograms have been moved to the Sequencer. These are combined together when the histograms are printed. Separate histograms are now maintained for tracking latency of all requests together, of hits only and of misses only. A particular set of histograms used to use the type GenericMachineType defined in one of the protocol files. This patch removes this type. Now, everything that relied on this type would use MachineType instead. To do this, SLICC has been changed so that multiple machine types can be declared by a controller in its preamble.
2013-06-24ruby: remove the three files related to profilingNilay Vaish
This patch removes the following three files: RubySlicc_Profiler.sm, RubySlicc_Profiler_interface.cc and RubySlicc_Profiler_interface.hh. Only one function prototyped in the file RubySlicc_Profiler.sm. Rest of the code appearing in any of these files is not in use. Therefore, these files are being removed. That one single function, profileMsgDelay(), is being moved to the protocol files where it is in use. If we need any of these deleted functions, I think the right way to make them visible is to have the AbstractController class in a .sm and let the controller state machine inherit from this class. The AbstractController class can then have the prototypes of these profiling functions in its definition.
2013-06-20ruby: fix typo in MOESI_CMP_token protocolLena Olson
2013-06-18ruby: Fix prefetching for MESI_CMP_DirectoryLena Olson
Transitions from present on PF_Ifetch were missing, causing a crash when prefetching is enabled. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-18ruby: restrict Address to being a type and not a variable nameLena Olson
Change all occurrances of Address as a variable name to instead use Addr. Address is an allowed name in slicc even when Address is also being used as a type, leading to declarations of "Address Address". While this works, it prevents adding another field of type Address because the compiler then thinks Address is a variable name, not type. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-05-21ruby: moesi hammer: cosmetic changesNilay Vaish
Updates copyright years, removes space at the end of lines, shortens variable names.
2013-05-21ruby: mesi cmp directory: cosmetic changesNilay Vaish
Updates copyright years, removes space at the end of lines, shortens variable names.
2013-05-21ruby: moesi cmp token: cosmetic changesNilay Vaish
Updates copyright years, removes space at the end of lines, shortens variable names.
2013-05-21ruby: moesi cmp directory: cosmetic changesNilay Vaish
Updates copyright years, removes space at the end of lines, shortens variable names.
2013-05-21ruby: add stats to .sm files, remove cache profilerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
This patch changes the way cache statistics are collected in ruby. As of now, there is separate entity called CacheProfiler which holds statistical variables for caches. The CacheMemory class defines different functions for accessing the CacheProfiler. These functions are then invoked in the .sm files. I find this approach opaque and prone to error. Secondly, we probably should not be paying the cost of a function call for recording statistics. Instead, this patch allows for accessing statistical variables in the .sm files. The collection would become transparent. Secondly, it would happen in place, so no function calls. The patch also removes the CacheProfiler class. --HG-- rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py
2013-04-23ruby: mesi coherence protocol: remove unused state M_MBNilay Vaish
2013-04-17ruby: moesi cmp directory: add copyright noticeNilay Vaish
2013-03-22ruby: remove unsued profile functionsNilay Vaish
2013-02-28ruby: mesi coherence protocol: invalidate lockDibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
The MESI CMP directory coherence protocol, while transitioning from SM to IM, did not invalidate the lock that it might have taken on a cache line. This patch adds an action for doing so. The problem was found by Dibakar, but I was not happy with his proposed solution. So I implemented a different solution. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-02-10ruby: MI protocol: add a missing transitionNilay Vaish
The transition for state MII and event Store was found missing during testing. The transition is being added. The controller will not stall the Store request in state MII
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
This patch is as of now the final patch in the series of patches that replace Time with Cycles.This patch further replaces Time with Cycles in Sequencer, Profiler, different protocols and related entities. Though Time has not been completely removed, the places where it is in use seem benign as of now.
2013-02-10ruby: replaces Time with Cycles in many placesNilay Vaish
The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
2013-02-10ruby: record fully busy cycle with in the controllerNilay Vaish
This patch does several things. First, the counter for fully busy cycles for a controller is now kept with in the controller, instead of being part of the profiler. Second, the topology class no longer keeps an array of controllers which was only used for printing stats. Instead, ruby system will now ask each controller to print the stats. Thirdly, the statistical variable for recording how many different types were created is being moved in to the controller from the profiler. Note that for printing, the profiler will collate results from different controllers.
2013-01-28ruby: remove get_time()Nilay Vaish
This patch replaces get_time() in *.sm files with curCycle() which is now possible since controllers are clocked objects.
2013-01-14Ruby: use ClockedObject in Consumer classNilay Vaish
Many Ruby structures inherit from the Consumer, which is used for scheduling events. The Consumer used to relay on an Event Manager for scheduling events and on g_system_ptr for time. With this patch, the Consumer will now use a ClockedObject to schedule events and to query for current time. This resulted in several structures being converted from SimObjects to ClockedObjects. Also, the MessageBuffer class now requires a pointer to a ClockedObject so as to query for time.
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
The patch adds support to slicc for recognizing arguments that should be passed to the constructor of a class. I did not like the fact that an explicit check was being carried on the type 'TBETable' to figure out the arguments to be passed to the constructor. The patch also moves some of the member variables that are declared for all the controllers to the base class AbstractController.
2012-10-18ruby: functional access updates to network test protocolNilay Vaish
I had forgotten to change the network test protocol while making changes to ruby for supporting functional accesses. This patch updates the protocol so that it can compile correctly.
2012-10-15ruby: improved support for functional accessesNilay Vaish
This patch adds support to different entities in the ruby memory system for more reliable functional read/write accesses. Only the simple network has been augmented as of now. Later on Garnet will also support functional accesses. The patch adds functional access code to all the different types of messages that protocols can send around. These messages are functionally accessed by going through the buffers maintained by the network entities. The patch also rectifies some of the bugs found in coherence protocols while testing the patch. With this patch applied, functional writes always succeed. But functional reads can still fail.
2012-10-15ruby: allow function definition in slicc structsNilay Vaish
This patch adds support for function definitions to appear in slicc structs. This is required for supporting functional accesses for different types of messages. Subsequent patches will use this to development.
2012-10-02ruby: rename template_hack to templateNilay Vaish
I don't like using the word hack. Hence, the patch.
2012-10-02ruby: remove unused code in protocolsNilay Vaish
2012-09-30MI coherence protocol: add copyright noticeNilay Vaish
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
Also allows for header files which are required in slicc generated code to be in a directory other than src/mem/ruby/slicc_interface.
2012-08-25MESI Protocol: Correct the virtual network in profile functionsNilay Vaish
The virtual network in a couple of places was incorrectly mentioned as 3 in place of 1. This is being corrected.
2012-08-25MESI Coherence Protocol: Add copyright noticeNilay Vaish
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-10ruby: banked cache array resource modelBrad Beckmann
This patch models a cache as separate tag and data arrays. The patch exposes the banked array as another resource that is checked by SLICC before a transition is allowed to execute. This is similar to how TBE entries and slots in output ports are modeled.
2012-07-10ruby: tag and data cache access supportJoel Hestness
Updates to Ruby to support statistics counting of cache accesses. This feature serves multiple purposes beyond simple stats collection. It provides the foundation for ruby to model the cache tag and data arrays as physical resources, as well as provide the necessary input data for McPAT power modeling.
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