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path: root/src/mem/protocol
AgeCommit message (Expand)Author
2017-04-05ruby: Fix MOESI_CMP_directory for new DMA status changes.Javier Cano-Cano
2016-11-19ruby: init MessageSizeType of SequencerMsg to Request_ControlSooraj Puthoor
2016-10-26ruby: Allow multiple outstanding DMA requestsMichael LeBeane
2016-10-06ruby: rename ALPHA_Network_test protocol to Garnet_standalone.Tushar Krishna
2016-04-26ruby: Rename pkt to m_pkt so it may be accessed via SLICCMatthew Poremba
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
2016-01-19* * *Tony Gutierrez
2015-07-20mem: misc flags for AMD gpu modelBlake Hechtman
2015-07-20ruby: slicc: have a static MachineTypeTony Gutierrez
2015-07-20ruby: slicc: remove support for single machine, multiple typesTony Gutierrez
2015-11-13slicc: fixes for the Address to Addr changeset (11025)Tony Gutierrez
2015-11-13ruby: add BoolVecJoe Gross
2015-09-23ruby: bloom filters: refactor codeNilay Vaish
2015-09-18ruby: print addresses in hexNilay Vaish
2015-09-16ruby: Add missing block deallocations in MOESI_hammerLena Olson
2015-09-16ruby: message buffer, timer table: significant changesNilay Vaish
2015-09-16slicc: export uint64_t instead of uint64Anthony Gutierrez
2015-09-05ruby: call setMRU from L1 controllers, not from sequencerNilay Vaish
2015-09-05ruby: declare all protocol message buffers as parametersNilay Vaish
2015-08-19ruby: reverts to changeset: bf82f1f7b040Nilay Vaish
2015-08-14ruby: add accessor functions to SLICC def of MachineIDNilay Vaish
2015-08-14ruby: call setMRU from L1 controllers, not from sequencerNilay Vaish
2015-08-14ruby: drop the [] notation for lookup function.Nilay Vaish
2015-08-14ruby: replace Address by AddrNilay Vaish
2015-08-14ruby: rename variables Addr to addrNilay Vaish
2015-08-14ruby: Protocol changes for SimObject MessageBuffersJoel Hestness
2015-08-14ruby: Expose MessageBuffers as SimObjectsJoel Hestness
2015-08-14ruby: Change PerfectCacheMemory::lookup to return pointerJoel Hestness
2015-08-03ruby: mesi three level: multiple corrections to the protocolNilay Vaish
2015-08-03ruby: mesi two,three level: copy data only when dirtyNilay Vaish
2015-07-20slicc: enable overloading in functions not in classesBrad Beckmann
2015-07-20ruby: adds size and empty apis to the msg buffer stallmapDavid Hashe
2015-07-20ruby: fix deadlock bug in banked array resource checksDavid Hashe
2015-07-20mem: add request types for acquire and releaseDavid Hashe
2015-07-20ruby: allocate a block in CacheMemory without updating LRU stateDavid Hashe
2015-07-20ruby: speed up function used for cache walksDavid Hashe
2015-07-20ruby: give access to cache tag/data latencies from SLICCDavid Hashe
2015-07-20slicc: support for multiple message types on the same bufferDavid Hashe
2015-07-20ruby: re-added the addressToInt slicc interface functionBrad Beckmann
2015-07-04ruby: drop NetworkMessage classNilay Vaish
2015-07-04ruby: mesi three level: name change to avoid clashNilay Vaish
2015-06-07ruby: Fix MESI consistency bugMarco Elver
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: coherence protocols: remove data block from dirctory entryNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-10-11ruby: mesi: slight renamingNilay Vaish
2014-09-01ruby: message buffers: significant changesNilay Vaish
2014-09-01ruby: slicc: change the way configurable members are specifiedNilay Vaish