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2011-06-08Ruby: Correctly set access permissions for directory entriesNilay Vaish
The access permissions for the directory entries are not being set correctly. This is because pointers are not used for handling directory entries. function. get and set functions for access permissions have been added to the Controller state machine. The changePermission() function provided by the AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC code once again. The set_permission() functionality has been removed. NOTE: Each protocol will have to define these get and set functions in order to compile successfully.
2011-05-20slicc: added vnet_type to MI_exampleTushar Krishna
Forgot to add this to MI_example in my previous patch.
2011-05-18slicc: added vnet_type field to identify response vnets from othersTushar Krishna
Identifying response vnets versus other vnets will allow garnet to determine which vnets will carry data packets, and which will carry ctrl packets, and use appropriate buffer sizes (since data packets are larger than ctrl packets). This in turn allows the orion power model to accurately estimate buffer power.
2011-04-28network: convert links & switches to first class C++ SimObjectsBrad Beckmann
This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. --HG-- rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
2011-04-01hammer: fixed dma uniproc errorBrad Beckmann
Fixed an error reguarding DMA for uninprocessor systems. Basically removed an overly agressive optimization that lead to inconsistent state between the cache and the directory.
2011-03-31CacheMemory: add allocateVoid() that is == allocate() but no return value.Lisa Hsu
This function duplicates the functionality of allocate() exactly, except that it does not return a return value. In protocols where you just want to allocate a block but do not want that block to be your implicitly passed cache_entry, use this function. Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(), and if you do a dummy assignment Entry foo := cache.allocate(address), the C++ compiler will complain of an unused variable. This is kind of a hack to get around those issues, but suggestions welcome.
2011-03-31Ruby: Add new object called WireBuffer to mimic a Wire.Lisa Hsu
This is a substitute for MessageBuffers between controllers where you don't want messages to actually go through the Network, because requests/responses can always get reordered wrt to one another (even if you turn off Randomization and turn on Ordered) because you are, after all, going through a network with contention. For systems where you model multiple controllers that are very tightly coupled and do not actually go through a network, it is a pain to have to write a coherence protocol to account for mixed up request/response orderings despite the fact that it's completely unrealistic. This is *not* meant as a substitute for real MessageBuffers when messages do in fact go over a network.
2011-03-31Ruby: pass Packet->Req->contextId() to Ruby.Lisa Hsu
It is useful for Ruby to understand from whence request packets came. This has all request packets going into Ruby pass the contextId value, if it exists. This supplants the old libruby proc_id value passed around in all the Messages, so I've also removed the unused unsigned proc_id; member generated by SLICC for all Message types.
2011-03-28This patch supports cache flushing in MOESI_hammerSomayeh Sardashti
2011-03-22Ruby: Remove CacheMsg class from SLICCNilay Vaish
The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object.
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
The tester code is in testers/networktest. The tester can be invoked by configs/example/ruby_network_test.py. A dummy coherence protocol called Network_test is also addded for network-only simulations and testing. The protocol takes in messages from the tester and just pushes them into the network in the appropriate vnet, without storing any state.
2011-03-19Ruby: Convert CacheRequestType to RubyRequestTypeNilay Vaish
This patch converts CacheRequestType to RubyRequestType so that both the protocol dependent and independent code makes use of the same request type.
2011-03-19Ruby: Convert AccessModeType to RubyAccessModeNilay Vaish
This patch converts AccessModeType to RubyAccessMode so that both the protocol dependent and independent code uses the same access mode.
2011-03-19MOESI_hammer: minor fixes to full-bit dirBrad Beckmann
2011-03-19MOESI_hammer: fixed dma bug with shared dataBrad Beckmann
2011-03-19MOESI_CMP_directory: significant dma bug fixesBrad Beckmann
2011-03-18SLICC: Remove external_type for structuresNilay Vaish
In SLICC, in order to define a type a data type for which it should not generate any code, the keyword external_type is used. For those data types for which code should be generated, the keyword structure is used. This patch eliminates the use of keyword external_type for defining structures. structure key word can now have an optional attribute external, which would be used for figuring out whether or not to generate the code for this structure. Also, now structures can have functions as well data members in them.
2011-03-18SLICC: Remove the keyword wake_up_dependentsNilay Vaish
In order to add stall and wait facility for protocols, a keyword wake_up_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call.
2011-03-18SLICC: Remove the keyword wake_up_all_dependentsNilay Vaish
In order to add stall and wait facility for protocols, a keyword wake_up_all_dependents was introduced. This patch removes the keyword, instead this functionality is now implemented as function call.
2011-03-17Ruby: expose a simple mod function in slicc interface.Lisa Hsu
2011-03-03SCons: Clean up some inconsistent capitalization in scons options.Gabe Black
2011-02-23ruby: automate permission settingBrad Beckmann
This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
2011-02-23MOESI_hammer: cache probe address clean upBrad Beckmann
2011-02-23ruby: cleaned up access permission enumBrad Beckmann
2011-02-23ruby: removed unsupported protocol filesBrad Beckmann
2011-02-22m5: merged in hammer fixBrad Beckmann
2011-02-19Ruby: Machine Type missing in MOESI CMP directory protocolNilay Vaish
In certain actions of the L1 cache controller, while creating an outgoing message, the machine type was not being set. This results in a segmentation fault when trace is collected. Joseph Pusudesris provided his patch for fixing this issue.
2011-02-19Ruby: clean MOESI CMP directory protocolNilay Vaish
The L1 cache controller file contains references to foo and goo queues, which are not in use at all. These have been removed.
2011-02-12Ruby: Reorder Cache Lookup in Protocol FilesNilay Vaish
The patch changes the order in which L1 dcache and icache are looked up when a request comes in. Earlier, if a request came in for instruction fetch, the dcache was looked up before the icache, to correctly handle self-modifying code. But, in the common case, dcache is going to report a miss and the subsequent icache lookup is going to report a hit. Given the invariant - caches under the same controller keep track of disjoint sets of cache blocks, we can move the icache lookup before the dcache lookup. In case of a hit in the icache, using our invariant, we know that the dcache would have reported a miss. In case of a miss in the icache, we know that icache would have missed even if the dcache was looked up before looking up the icache. Effectively, we are doing the same thing as before, though in the common case, we expect reduction in the number of lookups. This was empirically confirmed for MOESI hammer. The ratio lookups to access requests is now about 1.1 to 1.
2011-02-10MOESI_hammer: fixed wakeup for SS->S transistionBrad Beckmann
2011-02-08MESI CMP: Unset TBE pointer in L2 cache controllerNilay Vaish
The TBE pointer in the MESI CMP implementation was not being set to NULL when the TBE is deallocated. This resulted in segmentation fault on testing the protocol when the ProtocolTrace was switched on.
2011-02-06ruby: support to stallAndWait the mandatory queueBrad Beckmann
By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). --HG-- rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
2011-02-06MOESI_hammer: fixed dir bug counting received acksBrad Beckmann
2011-02-06MOESI_CMP_token: removed unused message fieldsTushar Krishna
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2011-02-06MOESI_hammer: trigge queue fix.Joel Hestness
2011-01-17Change interface between coherence protocols and CacheMemoryNilay Vaish
The purpose of this patch is to change the way CacheMemory interfaces with coherence protocols. Currently, whenever a cache controller (defined in the protocol under consideration) needs to carry out any operation on a cache block, it looks up the tag hash map and figures out whether or not the block exists in the cache. In case it does exist, the operation is carried out (which requires another lookup). As observed through profiling of different protocols, multiple such lookups take place for a given cache block. It was noted that the tag lookup takes anything from 10% to 20% of the simulation time. In order to reduce this time, this patch is being posted. I have to acknowledge that the many of the thoughts that went in to this patch belong to Brad. Changes to CacheMemory, TBETable and AbstractCacheEntry classes: 1. The lookup function belonging to CacheMemory class now returns a pointer to a cache block entry, instead of a reference. The pointer is NULL in case the block being looked up is not present in the cache. Similar change has been carried out in the lookup function of the TBETable class. 2. Function for setting and getting access permission of a cache block have been moved from CacheMemory class to AbstractCacheEntry class. 3. The allocate function in CacheMemory class now returns pointer to the allocated cache entry. Changes to SLICC: 1. Each action now has implicit variables - cache_entry and tbe. cache_entry, if != NULL, must point to the cache entry for the address on which the action is being carried out. Similarly, tbe should also point to the transaction buffer entry of the address on which the action is being carried out. 2. If a cache entry or a transaction buffer entry is passed on as an argument to a function, it is presumed that a pointer is being passed on. 3. The cache entry and the tbe pointers received __implicitly__ by the actions, are passed __explicitly__ to the trigger function. 4. While performing an action, set/unset_cache_entry, set/unset_tbe are to be used for setting / unsetting cache entry and tbe pointers respectively. 5. is_valid() and is_invalid() has been made available for testing whether a given pointer 'is not NULL' and 'is NULL' respectively. 6. Local variables are now available, but they are assumed to be pointers always. 7. It is now possible for an object of the derieved class to make calls to a function defined in the interface. 8. An OOD token has been introduced in SLICC. It is same as the NULL token used in C/C++. If you are wondering, OOD stands for Out Of Domain. 9. static_cast can now taken an optional parameter that asks for casting the given variable to a pointer of the given type. 10. Functions can be annotated with 'return_by_pointer=yes' to return a pointer. 11. StateMachine has two new variables, EntryType and TBEType. EntryType is set to the type which inherits from 'AbstractCacheEntry'. There can only be one such type in the machine. TBEType is set to the type for which 'TBE' is used as the name. All the protocols have been modified to conform with the new interface.
2011-01-13Ruby: Fixes MESI CMP directory protocolNilay Vaish
The current implementation of MESI CMP directory protocol is broken. This patch, from Arkaprava Basu, fixes the protocol.
2011-01-04Ruby: Updates MOESI Hammer protocolNilay Vaish
This patch changes the manner in which data is copied from L1 to L2 cache in the implementation of the Hammer's cache coherence protocol. Earlier, data was copied directly from one cache entry to another. This has been broken in to two parts. First, the data is copied from the source cache entry to a transaction buffer entry. Then, data is copied from the transaction buffer entry to the destination cache entry. This has been done to maintain the invariant - at any given instant, multiple caches under a controller are exclusive with respect to each other.
2010-12-22This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh ↵Nilay Vaish
file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
2010-12-01ruby: Converted old ruby debug calls to M5 debug callsNilay Vaish
This patch developed by Nilay Vaish converts all the old GEMS-style ruby debug calls to the appropriate M5 debug calls.
2010-08-24MOESI_hammer: fixed bug for dma reads in single cpu systemsBrad Beckmann
2010-08-20ruby: Added merge GETS optimization to hammerBrad Beckmann
Added an optimization that merges multiple pending GETS requests into a single request to the owner node.
2010-08-20ruby: Stall and wait input messages instead of recyclingBrad Beckmann
This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py
2010-08-20ruby: Recycle latency fix for hammerBrad Beckmann
Patch allows each individual message buffer to have different recycle latencies and allows the overall recycle latency to be specified at the cmd line. The patch also adds profiling info to make sure no one processor's requests are recycled too much.
2010-08-20MOESI_hammer: break down miss latency stalled cyclesBrad Beckmann
This patch tracks the number of cycles a transaction is delayed at different points of the request-forward-response loop.
2010-08-20ruby: added probe filter support to hammerBrad Beckmann
2010-08-20ruby: Disable migratory sharing for token and hammerBrad Beckmann
This patch allows one to disable migratory sharing for those cache blocks that are accessed by atomic requests. While the implementations are different between the token and hammer protocols, the motivation is the same. For Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that have been locked by LL accesses. Therefore, locked blocks should not transfer write permissions when responding to these load requests. Instead, only they only transfer read permissions so that the subsequent SC access can possibly succeed.
2010-08-20ruby: fixed token bugs associated with owner token countsBrad Beckmann
This patch fixes several bugs related to previous inconsistent assumptions on how many tokens the Owner had. Mike Marty should have fixes these bugs years ago. :)
2010-08-20ruby: MOESI_CMP_token dma fixesBrad Beckmann
This patch fixes various protocol bugs regarding races between dma requests and persistent requests.