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path: root/src/mem/qport.hh
AgeCommit message (Expand)Author
2015-11-06mem: Enforce insertion order on the cache response pathAli Jafri
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-03-02mem: Add option to force in-order insertion in PacketQueueStephan Diestelhorst
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2014-02-23ruby: Simplify RubyPort flow control and routingAndreas Hansson
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson