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path: root/src/mem/request.hh
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2015-01-22mem: Clean up Request initialisationAndreas Hansson
This patch tidies up how we create and set the fields of a Request. In essence it tries to use the constructor where possible (as opposed to setPhys and setVirt), thus avoiding spreading the information across a number of locations. In fact, setPhys is made private as part of this patch, and a number of places where we callede setVirt instead uses the appropriate constructor.
2014-12-02mem: Make Request getters constAndreas Hansson
This patch tidies up the Request class, making all getters const. The odd one out is incAccessDepth which is called by the memory system as packets carry the request around. This is also const to enable the packet to hold on to a const Request.
2014-09-09mem: Add accessor function for vaddrMitch Hayenga
Determine if a request has an associated virtual address.
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
Static analysis unearther a bunch of uninitialised variables and members, and this patch addresses the problem. In all cases these omissions seem benign in the end, but at least fixing them means less false positives next time round.
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
This patch extends the classic prefetcher to work on non-block aligned addresses. Because the existing prefetchers in gem5 mask off the lower address bits of cache accesses, many predictable strides fail to be detected. For example, if a load were to stride by 48 bytes, with 64 byte cachelines, the current stride based prefetcher would see an access pattern of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This patch fixes this, by training the prefetcher on access and not masking off the lower address bits. It also adds the following configuration options: 1) Training/prefetching only on cache misses, 2) Training/prefetching only on data acceses, 3) Optionally tagging prefetches with a PC address. #3 allows prefetchers to train off of prefetch requests in systems with multiple cache levels and PC-based prefetchers present at multiple levels. It also effectively allows a pipelining of prefetch requests (like in POWER4) across multiple levels of cache hierarchy. Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean).
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24mem: Add flag to request if it was generated by a page table walkGiacomo Gabrielli
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning secure and non-secure memory accesses.
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump.
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
Add some values and methods to the request object to track the translation and access latency for a request and which level of the cache hierarchy responded to the request.
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
This patch adds a flag in the request class that indicates if the request was made in privileged mode.
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
ASI_BITS in the Request object were originally used to store a memory request's ASI on SPARC. This is not the case any more since other ISAs use the ASI bits to store architecture-dependent information. This changeset renames the ASI_BITS to ARCH_BITS which better describes their use. Additionally, the getAsi() accessor is renamed to getArchFlags().
2013-10-15mem: Use a flag instead of address bit 63 for generic IPRsAndreas Sandberg
Using address bit 63 to identify generic IPRs caused problems on SPARC, where IPRs are heavily used. This changeset redefines how generic IPRs are identified. Instead of using bit 63, we now use a separate flag (GENERIC_IPR) a memory request.
2013-06-18kvm: Use the address finalization code in the TLBAndreas Sandberg
Reuse the address finalization code in the TLB instead of replicating it when handling MMIO. This patch also adds support for injecting memory mapped IPR requests into the memory system.
2012-11-02ARM: dump stats and process info on context switchesDam Sunwoo
This patch enables dumping statistics and Linux process information on context switch boundaries (__switch_to() calls) that are used for Streamline integration (a graphical statistics viewer from ARM).
2012-06-05sim: Remove FastAllocAli Saidi
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe. After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc when running twolf for ARM.
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
This patch fixes the cache stats to use the new request ids. Cache stats also display the requestor names in the vector subnames. Most cache stats now include "nozero" and "nonan" flags to reduce the amount of excessive cache stat dump. Also, simplified incMissCount()/incHitCount() functions.
2012-02-12mem: Add a master ID to each request object.Ali Saidi
This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
2011-09-13Mem: Allow ASID to be set after request is created.Daniel Johnson
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2010-10-16Mem: Reclaim some request flags used by MIPS for alignment checking.Gabe Black
These flags were being used to identify what alignment a request needed, but the same information is available using the request size. This change also eliminates the isMisaligned function. If more complicated alignment checks are needed, they can be signaled using the ASI_BITS space in the flags vector like is currently done with ARM.
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches ↵Gene Wu
when it in received
2010-01-29ruby: added the GEMS ruby testerBrad Beckmann
2009-11-10Mem: Eliminate the NO_FAULT request flag.Gabe Black
2009-08-01Clean up some inconsistencies with Request flags.Steve Reinhardt
2009-08-01Rename internal Request fields to start with '_'.Steve Reinhardt
The inconsistency was causing a subtle bug with some of the constructors where the params had the same name as the fields. This is also a first step to switching the accessors over to our new "standard", e.g., getVaddr() -> vaddr().
2009-05-29request: add accessor and constructor for setting time other than curTickNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-04-23request: reorganize flags to group related flags together.Steve Reinhardt
2009-04-21request: add PREFETCH flag.Steve Reinhardt
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-04-20request: split public and private flags into separate fields.Steve Reinhardt
This frees up needed space for more public flags. Also: - remove unused Request accessor methods - make Packet use public Request accessors, so it need not be a friend
2009-04-19Mem: Fill out the comment that describes the LOCKED request flag.Gabe Black
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Add a LOCKED flag back in for x86 style locking.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-03-10prefetch: don't panic on requests w/o contextID (e.g., writebacks).Steve Reinhardt
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2009-02-16Fixes to get prefetching working again.Steve Reinhardt
Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
2008-12-06flags: Change naming of functions to be clearerNathan Binkert
2008-11-14Fix a bunch of bugs I introduced when I changed the flags stuff for packets.Nathan Binkert
I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class.
2008-11-13CPU: Refactor read/write in the simple timing CPU.Gabe Black
2008-11-10style: clean up the Packet stuffNathan Binkert
2008-11-10mem: Assert that requests have non-negative size.Steve Reinhardt
Would have saved me much debugging time if these had been in there previously.
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-10-09mem: Add a method for setting the time on a packet.Nathan Binkert
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵Ali Saidi
should configure their editors to not insert tabs