gem5 - gem5

Age	Commit message (Expand)	Author
2015-09-05	ruby: call setMRU from L1 controllers, not from sequencer	Nilay Vaish
2015-08-29	ruby: eliminate type uint64 and int64	Nilay Vaish
2015-08-27	ruby: handle llsc accesses through CacheEntry, not CacheMemory	Nilay Vaish
2015-08-19	ruby: reverts to changeset: bf82f1f7b040	Nilay Vaish
2015-08-14	ruby: cache memory: drop {try,test}CacheAccess functions	Nilay Vaish
2015-08-14	ruby: call setMRU from L1 controllers, not from sequencer	Nilay Vaish
2015-08-14	ruby: eliminate type uint64 and int64	Nilay Vaish
2015-08-14	ruby: handle llsc accesses through CacheEntry, not CacheMemory	Nilay Vaish
2015-08-14	ruby: replace Address by Addr	Nilay Vaish
2015-08-14	ruby: Remove the RubyCache/CacheMemory latency	Joel Hestness
2015-07-20	ruby: expose access permission to replacement policies	David Hashe
2015-07-20	ruby: fix deadlock bug in banked array resource checks	David Hashe
2015-07-20	ruby: allocate a block in CacheMemory without updating LRU state	David Hashe
2015-07-20	ruby: speed up function used for cache walks	David Hashe
2015-07-20	ruby: initialize replacement policies with their own simobjs	David Hashe
2015-07-20	ruby: give access to cache tag/data latencies from SLICC	David Hashe
2014-10-11	ruby: structures: coorect #ifndef macros in header files	Nilay Vaish
2014-09-01	ruby: remove typedef of Index as int64	Nilay Vaish
2014-09-01	ruby: move files from ruby/system to ruby/structures	Nilay Vaish