Age | Commit message (Expand) | Author |
2014-11-18 | power: Add power states to ClockedObject | Akash Bagdia |
2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
2016-01-19 | gpu-compute: AMD's baseline GPU model | Tony Gutierrez |
2016-01-11 | scons: Enable -Wextra by default | Andreas Hansson |
2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
2015-09-29 | ruby: Fix CacheMemory allocate leak | Joel Hestness |
2015-09-29 | ruby: RubyMemoryControl delete requests | Joel Hestness |
2015-09-18 | ruby: print addresses in hex | Nilay Vaish |
2015-09-17 | ruby: update WireBuffer API to match that of MessageBuffer | Tony Gutierrez |
2015-09-16 | ruby: message buffer, timer table: significant changes | Nilay Vaish |
2015-09-16 | ruby: rename System.{hh,cc} to RubySystem.{hh,cc} | David Hashe |
2015-09-05 | ruby: call setMRU from L1 controllers, not from sequencer | Nilay Vaish |
2015-09-05 | ruby: adds set and way indices to AbstractCacheEntry | Nilay Vaish |
2015-09-01 | ruby: directory memory: drop unused variable. | Nilay Vaish |
2015-08-29 | ruby: eliminate type uint64 and int64 | Nilay Vaish |
2015-08-27 | ruby: handle llsc accesses through CacheEntry, not CacheMemory | Nilay Vaish |
2015-08-21 | ruby: Move Rubys cache class from Cache.py to RubyCache.py | Andreas Hansson |
2015-08-19 | ruby: reverts to changeset: bf82f1f7b040 | Nilay Vaish |
2015-08-14 | ruby: directory memory: drop unused variable. | Nilay Vaish |
2015-08-14 | ruby: cache memory: drop {try,test}CacheAccess functions | Nilay Vaish |
2015-08-14 | ruby: call setMRU from L1 controllers, not from sequencer | Nilay Vaish |
2015-08-14 | ruby: adds set and way indices to AbstractCacheEntry | Nilay Vaish |
2015-08-14 | ruby: eliminate type uint64 and int64 | Nilay Vaish |
2015-08-14 | ruby: slicc: use default argument value | Nilay Vaish |
2015-08-14 | ruby: handle llsc accesses through CacheEntry, not CacheMemory | Nilay Vaish |
2015-08-14 | ruby: replace Address by Addr | Nilay Vaish |
2015-08-14 | ruby: Change PerfectCacheMemory::lookup to return pointer | Joel Hestness |
2015-08-14 | ruby: Remove the RubyCache/CacheMemory latency | Joel Hestness |
2015-07-20 | ruby: expose access permission to replacement policies | David Hashe |
2015-07-20 | ruby: fix deadlock bug in banked array resource checks | David Hashe |
2015-07-20 | ruby: allocate a block in CacheMemory without updating LRU state | David Hashe |
2015-07-20 | ruby: speed up function used for cache walks | David Hashe |
2015-07-20 | ruby: initialize replacement policies with their own simobjs | David Hashe |
2015-07-20 | ruby: give access to cache tag/data latencies from SLICC | David Hashe |
2015-07-10 | ruby: replace global g_abs_controls with per-RubySystem var | Brandon Potter |
2015-07-10 | ruby: replace global g_system_ptr with per-object pointers | Brandon Potter |
2015-07-10 | ruby: remove extra whitespace and correct misspelled words | Brandon Potter |
2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
2015-07-04 | ruby: drop NetworkMessage class | Nilay Vaish |
2015-07-04 | ruby: remove message buffer node | Nilay Vaish |
2015-05-26 | ruby: Deprecation warning for RubyMemoryControl | Andreas Hansson |
2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
2014-11-06 | ruby: interface with classic memory controller | Nilay Vaish |
2014-11-06 | ruby: coherence protocols: remove data block from dirctory entry | Nilay Vaish |
2014-11-06 | ruby: remove sparse memory. | Nilay Vaish |
2014-10-16 | mem: Dynamically determine page bytes in memory components | Andreas Hansson |
2014-10-11 | ruby: structures: coorect #ifndef macros in header files | Nilay Vaish |
2014-09-03 | base: Use the global Mersenne twister throughout | Andreas Hansson |
2014-09-01 | ruby: remove typedef of Index as int64 | Nilay Vaish |