gem5 - gem5

Age	Commit message (Expand)	Author
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-03-17	ruby: remove some of the unnecessary code	Nilay Vaish
2014-02-23	ruby: route all packets through ruby port	Nilay Vaish
2014-02-23	ruby: Simplify RubyPort flow control and routing	Andreas Hansson
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-04-22	mem: Replace check with panic where inhibited should not happen	Andreas Hansson
2013-04-09	Ruby: Fix RubyPort evict packet memory leak	Joel Hestness
2013-02-19	scons: Fix warnings issued by clang 3.2svn (XCode 4.6)	Andreas Hansson
2013-02-19	mem: Add predecessor to SenderState base class	Andreas Hansson
2013-02-10	ruby: enable multiple clock domains	Nilay Vaish
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-02	ruby: move functional access to ruby system	Nilay Vaish
2012-09-23	RubyPort and Sequencer: Fix draining	Joel Hestness
2012-09-11	Ruby: Use uint8_t instead of uint8 everywhere	Nilay Vaish
2012-09-10	Ruby System: Convert to Clocked Object	Nilay Vaish
2012-08-27	Ruby: Remove RubyEventQueue	Nilay Vaish
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-09	Port: Add isSnooping to slave port (asking master port)	Andreas Hansson
2012-05-04	Ruby: Ensure snoop requests are sent using sendTimingSnoopReq	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-02	Ruby: Rename RubyPort::sendTiming to avoid overriding base class	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-01-30	MEM: Make the RubyPort physMemPort a PioPort instead of M5Port	Andreas Hansson
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-11	Ruby: Resurrect Cache Warmup Capability	Nilay Vaish
2012-01-11	Ruby Port: Add a list of cpu ports attached to this port	Nilay Vaish
2011-11-14	Ruby: Process packet instead of RubyRequest in Sequencer	Nilay Vaish
2011-09-01	Functional Accesses: Update states to support Broadcast/Snooping protocols.	Lisa Hsu
2011-08-15	Ruby: Initialize some variables.	Nilay Vaish
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-28	This patch supports cache flushing in MOESI_hammer	Somayeh Sardashti
2011-03-22	Ruby: Remove CacheMsg class from SLICC	Nilay Vaish
2011-03-19	Ruby: dma retry fix	Brad Beckmann
2011-03-19	RubyPort: minor fixes to trace flag and dprintfs	Brad Beckmann