gem5 - gem5

Age	Commit message (Collapse)	Author
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
	This patch introduces the notion of a master and slave port in the C++ code, thus bringing the previous classification from the Python classes into the corresponding simulation objects and memory objects. The patch enables us to classify behaviours into the two bins and add assumptions and enfore compliance, also simplifying the two interfaces. As a starting point, isSnooping is confined to a master port, and getAddrRanges to slave ports. More of these specilisations are to come in later patches. The getPort function is not getMasterPort and getSlavePort, and returns a port reference rather than a pointer as NULL would never be a valid return value. The default implementation of these two functions is placed in MemObject, and calls fatal. The one drawback with this specific patch is that it requires some code duplication, e.g. QueuedPort becomes QueuedMasterPort and QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort (avoiding multiple inheritance). With the later introduction of the port interfaces, moving the functionality outside the port itself, a lot of the duplicated code will disappear again.
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
	This patch decouples the queueing and the port interactions to simplify the introduction of the master and slave ports. By separating the queueing functionality from the port itself, it becomes much easier to distinguish between master and slave ports, and still retain the queueing ability for both (without code duplication). As part of the split into a PacketQueue and a port, there is now also a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The QueuedPort is useful for ports that want to leave the packet transmission of outgoing packets to the queue and is used by both master and slave ports. The SimpleTimingPort inherits from the QueuedPort and adds the implemention of recvTiming and recvFunctional through recvAtomic. The PioPort and MessagePort are cleaned up as part of the changes. --HG-- rename : src/mem/tport.cc => src/mem/packet_queue.cc rename : src/mem/tport.hh => src/mem/packet_queue.hh
2012-03-02	Ruby: Rename RubyPort::sendTiming to avoid overriding base class	Andreas Hansson
	This patch renames the sendTiming member function in the RubyPort to avoid inadvertently hiding Port::sendTiming (discovered through some rather painful debugging). The RubyPort does, in fact, rely on the functionality of the queued port and the implementation merely schedules a send the next cycle. The new name for the member function is sendNextCycle to better reflect this behaviour. In the unlikely event that we ever shift to using C++11 the member functions in Port should have a "final" identifier to prevent any overriding in derived classes.
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
	This patch moves all port creation from the getPort method to be consistently done in the MemObject's constructor. This is possible thanks to the Swig interface passing the length of the vector ports. Previously there was a mix of: 1) creating the ports as members (at object construction time) and using getPort for the name resolution, or 2) dynamically creating the ports in the getPort call. This is now uniform. Furthermore, objects that would not be complete without a port have these ports as members rather than having pointers to dynamically allocated ports. This patch also enables an elaboration-time enumeration of all the ports in the system which can be used to determine the masterId.
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
	This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
	This change adds a master id to each request object which can be used identify every device in the system that is capable of issuing a request. This is part of the way to removing the numCpus+1 stats in the cache and replacing them with the master ids. This is one of a series of changes that make way for the stats output to be changed to python.
2012-01-30	MEM: Make the RubyPort physMemPort a PioPort instead of M5Port	Andreas Hansson
	This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system.
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
	This patch implements the functionality for forwarding invalidations and replacements from the L1 cache of the Ruby memory system to the O3 CPU. The implementation adds a list of ports to RubyPort. Whenever a replacement or an invalidation is performed, the L1 cache forwards this to all the ports, which is the LSQ in case of the O3 CPU.
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
	The functional ports are no longer used and this patch cleans up the legacy that is still present in buses, memories, CPUs etc. Note that this does not refer to the class FunctionalPort (already removed), but rather ports with the name (and use) functional.
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
	This patch simplifies the address-range determination mechanism and also unifies the naming across ports and devices. It further splits the queries for determining if a port is snooping and what address ranges it responds to (aiming towards a separation of cache-maintenance ports and pure memory-mapped ports). Default behaviours are such that most ports do not have to define isSnooping, and master ports need not implement getAddrRanges.
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
	Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
2012-01-11	Ruby: Resurrect Cache Warmup Capability	Nilay Vaish
	This patch resurrects ruby's cache warmup capability. It essentially makes use of all the infrastructure that was added to the controllers, memories and the cache recorder.
2012-01-11	Ruby Port: Add a list of cpu ports attached to this port	Nilay Vaish

2011-11-14	Ruby: Process packet instead of RubyRequest in Sequencer	Nilay Vaish
	This patch changes the implementation of Ruby's recvTiming() function so that it pushes a packet in to the Sequencer instead of a RubyRequest. This requires changes in the Sequencer's makeRequest() and issueRequest() functions, as they also need to operate on a Packet instead of RubyRequest.
2011-09-01	Functional Accesses: Update states to support Broadcast/Snooping protocols.	Lisa Hsu
	In the current implementation of Functional Accesses, it's very hard to implement broadcast or snooping protocols where the memory has no idea if it has exclusive access to a cache block or not. Without this knowledge, making sure the RW vs. RO permissions are right are next to impossible. So we add a new state called Backing_Store to enable the conveyance that this is the backup storage for a block, so that it can be written if it is the only possibly RW block in the system, or written even if there is another RW block in the system, without causing problems. Also, a small change to actually set the m_name field for each Controller so that debugging can be easier. Now you can access a controller's name just by controller->getName().
2011-08-15	Ruby: Initialize some variables.	Nilay Vaish

2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
	This patch rpovides functional access support in Ruby. Currently only the M5Port of RubyPort supports functional accesses. The support for functional through the PioPort will be added as a separate patch.
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
	At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15	includes: sort all includes	Nathan Binkert

2011-03-28	This patch supports cache flushing in MOESI_hammer	Somayeh Sardashti

2011-03-22	Ruby: Remove CacheMsg class from SLICC	Nilay Vaish
	The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object.
2011-03-19	Ruby: dma retry fix	Brad Beckmann
	This patch fixes the problem where Ruby would fail to call sendRetry on ports after it nacked the port. This patch is particularly helpful for bursty dma requests which often include several packets.
2011-03-19	RubyPort: minor fixes to trace flag and dprintfs	Brad Beckmann

2011-02-09	ruby: removed duplicate make response call	Brad Beckmann

2011-02-06	mem: Added support for Null data packet	Brad Beckmann
	The packet now identifies whether static or dynamic data has been allocated and is used by Ruby to determine whehter to copy the data pointer into the ruby request. Subsequently, Ruby can be told not to update phys memory when receiving packets.
2011-02-06	ruby: Fix RubyPort to properly handle retrys	Brad Beckmann

2011-02-06	Ruby: Fix to return cache block size to CPU for split data transfers	Joel Hestness

2011-02-06	Ruby: Add support for locked memory accesses in X86_FS	Joel Hestness

2011-02-06	Ruby: Update the Ruby request type names for LL/SC	Joel Hestness

2011-02-06	ruby: Assert for x86 misaligned access	Brad Beckmann
	This patch ensures only aligned access are passed to ruby and includes a fix to the DPRINTF address print.
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
	This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2010-08-24	testers: move testers to a new directory	Brad Beckmann
	This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. --HG-- rename : configs/example/determ_test.py => configs/example/ruby_direct_test.py rename : src/cpu/directedtest/DirectedGenerator.cc => src/cpu/testers/directedtest/DirectedGenerator.cc rename : src/cpu/directedtest/DirectedGenerator.hh => src/cpu/testers/directedtest/DirectedGenerator.hh rename : src/cpu/directedtest/InvalidateGenerator.cc => src/cpu/testers/directedtest/InvalidateGenerator.cc rename : src/cpu/directedtest/InvalidateGenerator.hh => src/cpu/testers/directedtest/InvalidateGenerator.hh rename : src/cpu/directedtest/RubyDirectedTester.cc => src/cpu/testers/directedtest/RubyDirectedTester.cc rename : src/cpu/directedtest/RubyDirectedTester.hh => src/cpu/testers/directedtest/RubyDirectedTester.hh rename : src/cpu/directedtest/RubyDirectedTester.py => src/cpu/testers/directedtest/RubyDirectedTester.py rename : src/cpu/directedtest/SConscript => src/cpu/testers/directedtest/SConscript rename : src/cpu/directedtest/SeriesRequestGenerator.cc => src/cpu/testers/directedtest/SeriesRequestGenerator.cc rename : src/cpu/directedtest/SeriesRequestGenerator.hh => src/cpu/testers/directedtest/SeriesRequestGenerator.hh rename : src/cpu/memtest/MemTest.py => src/cpu/testers/memtest/MemTest.py rename : src/cpu/memtest/SConscript => src/cpu/testers/memtest/SConscript rename : src/cpu/memtest/memtest.cc => src/cpu/testers/memtest/memtest.cc rename : src/cpu/memtest/memtest.hh => src/cpu/testers/memtest/memtest.hh rename : src/cpu/rubytest/Check.cc => src/cpu/testers/rubytest/Check.cc rename : src/cpu/rubytest/Check.hh => src/cpu/testers/rubytest/Check.hh rename : src/cpu/rubytest/CheckTable.cc => src/cpu/testers/rubytest/CheckTable.cc rename : src/cpu/rubytest/CheckTable.hh => src/cpu/testers/rubytest/CheckTable.hh rename : src/cpu/rubytest/RubyTester.cc => src/cpu/testers/rubytest/RubyTester.cc rename : src/cpu/rubytest/RubyTester.hh => src/cpu/testers/rubytest/RubyTester.hh rename : src/cpu/rubytest/RubyTester.py => src/cpu/testers/rubytest/RubyTester.py rename : src/cpu/rubytest/SConscript => src/cpu/testers/rubytest/SConscript
2010-08-20	ruby: Fixed RubyPort sendTiming callbacks	Brad Beckmann
	Fixed RubyPort schedSendTiming calls to match ruby frequency.
2010-08-20	ruby: fix ruby llsc support to sync sc outcomes	Brad Beckmann
	Added support so that ruby can determine the outcome of store conditional operations and reflect that outcome to M5 physical memory and cpus.
2010-03-22	ruby: style pass	Nathan Binkert

2010-03-22	ruby: improved isReadWrite fix me comment	Brad Beckmann

2010-03-21	ruby: Ruby support for LLSC	Brad Beckmann

2010-01-29	ruby: Removed static members in RubyPort including hitcallback	Brad Beckmann
	Removed static members in RubyPort and removed the ruby request unique id.
2010-01-29	ruby: added the GEMS ruby tester	Brad Beckmann

2010-01-29	ruby: FS support using the new configuration system	Brad Beckmann

2010-01-29	ruby: Ruby changes required to use the python config system	Brad Beckmann
	This patch includes the necessary changes to connect ruby objects using the python configuration system. Mainly it consists of removing unnecessary ruby object pointers and connecting the necessary object pointers using the generated param objects. This patch includes the slicc changes necessary to connect generated ruby objects together using the python configuraiton system.
2010-01-29	ruby: Convert most Ruby objects to M5 SimObjects.	Steve Reinhardt
	The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
2009-07-06	ruby: Import the latest ruby changes from gems.	Nathan Binkert
	This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore.