gem5 - gem5

Age	Commit message (Expand)	Author
2019-03-20	invisispec-1.0 source	Iru Cai
2017-12-15	mem-ruby: Support atomic_noncaching acceses in ruby	Swapnil Haria
2016-02-18	ruby: move range change send from RubyPort to derived classes.	Tony Gutierrez
2016-01-19	gpu-compute: AMD's baseline GPU model	Tony Gutierrez
2015-07-20	ruby: more flexible ruby tester support	Brad Beckmann
2015-10-12	misc: Add explicit overrides and fix other clang >= 3.5 issues	Andreas Hansson
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-09-16	ruby: rename System.{hh,cc} to RubySystem.{hh,cc}	David Hashe
2015-08-14	ruby: replace Address by Addr	Nilay Vaish
2015-07-10	ruby: replace global g_system_ptr with per-object pointers	Brandon Potter
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-06-25	Ruby: Remove assert in RubyPort retry list logic	Jason Power
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2014-11-06	ruby: provide a backing store	Nilay Vaish
2014-10-16	arch,x86,mem: Dynamically determine the ISA for Ruby store check	Andreas Hansson
2014-09-01	ruby: move files from ruby/system to ruby/structures	Nilay Vaish
2014-03-17	ruby: remove some of the unnecessary code	Nilay Vaish
2014-02-23	ruby: route all packets through ruby port	Nilay Vaish
2014-02-23	ruby: Simplify RubyPort flow control and routing	Andreas Hansson
2014-01-10	ruby: move all statistics to stats.txt, eliminate ruby.stats	Nilay Vaish
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-02-19	scons: Fix warnings issued by clang 3.2svn (XCode 4.6)	Andreas Hansson
2013-02-19	mem: Add predecessor to SenderState base class	Andreas Hansson
2013-02-10	ruby: enable multiple clock domains	Nilay Vaish
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-02	ruby: move functional access to ruby system	Nilay Vaish
2012-09-23	RubyPort and Sequencer: Fix draining	Joel Hestness
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	Ruby: Remove the physMemPort and instead access memory directly	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-02	Ruby: Rename RubyPort::sendTiming to avoid overriding base class	Andreas Hansson
2012-02-24	MEM: Move port creation to the memory object(s) construction	Andreas Hansson
2012-01-30	MEM: Make the RubyPort physMemPort a PioPort instead of M5Port	Andreas Hansson
2012-01-23	O3, Ruby: Forward invalidations from Ruby to O3 CPU	Nilay Vaish
2012-01-11	Ruby: Resurrect Cache Warmup Capability	Nilay Vaish
2012-01-11	Ruby Port: Add a list of cpu ports attached to this port	Nilay Vaish
2011-11-14	Ruby: Process packet instead of RubyRequest in Sequencer	Nilay Vaish
2011-06-30	Ruby: Add support for functional accesses	Brad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-04-15	includes: sort all includes	Nathan Binkert
2011-02-25	Ruby: Remove libruby	Nilay Vaish
2011-02-06	mem: Added support for Null data packet	Brad Beckmann
2011-02-06	ruby: Fix RubyPort to properly handle retrys	Brad Beckmann
2011-02-06	Ruby: Fix to return cache block size to CPU for split data transfers	Joel Hestness
2010-04-02	ruby: get "using namespace" out of headers	Nathan Binkert