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path: root/src/mem/ruby/system/Sequencer.py
AgeCommit message (Expand)Author
2015-08-14ruby: Remove the RubyCache/CacheMemory latencyJoel Hestness
2015-07-10ruby: replace global g_system_ptr with per-object pointersBrandon Potter
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
2014-11-06ruby: provide a backing storeNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-11-06ruby: dma sequencer: remove RubyPort as parent classNilay Vaish
2014-02-23ruby: route all packets through ruby portNilay Vaish
2013-03-06ruby: remove the functional copy of memory in se modeNilay Vaish
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2011-06-30Ruby: Add support for functional accessesBrad Beckmann ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2011-03-21This patch adds the network tester for simple and garnet networks.Tushar Krishna
2011-02-06mem: Added support for Null data packetBrad Beckmann
2011-02-06ruby: Fix RubyPort to properly handle retrysBrad Beckmann
2010-03-21ruby: Added copyright to many Ruby *.py filesBrad Beckmann
2010-01-29ruby: added the GEMS ruby testerBrad Beckmann
2010-01-29ruby: FS support using the new configuration systemBrad Beckmann
2010-01-29ruby: Ruby changes required to use the python config systemBrad Beckmann
2010-01-29ruby: Convert most Ruby objects to M5 SimObjects.Steve Reinhardt