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Previously, the set size was set to 4. This was mostly do to the fact that a
crazy graduate student use to create networks with 256 l2 cache banks. Now it
is far more likely that users will create systems with less than 64 of any
particular controller type. Therefore Ruby should be optimized for a set size
of 1.
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The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory
data array.
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The patch includes direct support for the MI example protocol.
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Mostly files missed during import or screwed up during import
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It's a power of two anyway, so why use it in the first place.
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Do not use "using namespace std;" in headers
Include header files as needed
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Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.
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Removed static members in RubyPort and removed the ruby request unique id.
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Removed the old config interface from RubySystem and libruby.
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Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
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Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively. Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects. This
simplifies the creation of these profilers.
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removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable
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Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
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Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer. As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.
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This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system. Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector. Eventually this support should be removed from the main
profiler and go into a separate object. Each memory controller should have
a pointer to that new mem_cntrl profile object.
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Wrapped ruby events using the m5 event object. Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.
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As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
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This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
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rather than in RubySystem object.
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The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
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This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
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These files are need by the MOESI_CMP_token protocol.
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Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
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Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
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Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
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