gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-07-03	mem: Split WriteInvalidateReq into write and invalidate	Andreas Hansson
2015-06-25	Ruby: Remove assert in RubyPort retry list logic	Jason Power
2015-05-19	ruby: Fix RubySystem warm-up and cool-down scope	Joel Hestness
2015-03-23	mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW	Steve Reinhardt
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-26	Ruby: Update backing store option to propagate through to all RubyPorts	Jason Power
2015-01-22	mem: Always use SenderState for response routing in RubyPort	Andreas Hansson
2015-01-22	mem: Clean up Request initialisation	Andreas Hansson
2014-12-02	mem: Add const getters for write packet data	Andreas Hansson
2014-12-02	mem: Remove null-check bypassing in Packet::getPtr	Andreas Hansson
2014-11-06	ruby: provide a backing store	Nilay Vaish
2014-11-06	ruby: interface with classic memory controller	Nilay Vaish
2014-11-06	ruby: coherence protocols: remove data block from dirctory entry	Nilay Vaish
2014-11-06	ruby: remove sparse memory.	Nilay Vaish
2014-11-06	ruby: single physical memory in fs mode	Nilay Vaish
2014-11-06	ruby: dma sequencer: remove RubyPort as parent class	Nilay Vaish
2014-10-16	misc: Move AddrRangeList from port.hh to addr_range.hh	Andreas Hansson
2014-10-16	mem: Use shared_ptr for Ruby Message classes	Andreas Hansson
2014-10-16	arch,x86,mem: Dynamically determine the ISA for Ruby store check	Andreas Hansson
2014-10-01	misc: Fix issues identified by static analysis	Andreas Hansson
2014-09-27	misc: Fix a bunch of minor issues identified by static analysis	Andreas Hansson
2014-09-01	ruby: eliminate type Time	Nilay Vaish
2014-09-01	ruby: move files from ruby/system to ruby/structures	Nilay Vaish
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2014-04-19	ruby: recorder: Fix (de-)serializing with different cache block-sizes	Marco Elver
2014-03-20	ruby: no piobus in se mode	Nilay Vaish
2014-03-17	ruby: remove some of the unnecessary code	Nilay Vaish
2014-02-23	ruby: route all packets through ruby port	Nilay Vaish
2014-02-23	ruby: Simplify RubyPort flow control and routing	Andreas Hansson
2014-02-23	ruby: remove few not required #includes	Nilay Vaish
2014-02-21	ruby: cache: remove not required variable m_cache_name	Nilay Vaish
2014-02-20	ruby: message buffer: removes some unecessary functions.	Nilay Vaish
2014-02-06	ruby: memory controller: use MemoryNode *	Nilay Vaish
2014-01-10	ruby: move all statistics to stats.txt, eliminate ruby.stats	Nilay Vaish
2014-01-04	ruby: some small changes	Nilay Vaish
2013-10-15	ruby: eliminate non-determinism from ruby.stats output	Steve Reinhardt
2013-09-06	ruby: network: convert to gem5 style stats	Nilay Vaish
2013-09-06	ruby: converts sparse memory stats to gem5 style	Nilay Vaish
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-06-27	sim: Add the notion of clock domains to all ClockedObjects	Akash Bagdia
2013-06-27	config: Remove redundant explicit setting of default clocks	Akash Bagdia
2013-06-25	ruby: profiler: lots of inter-related changes	Nilay Vaish
2013-06-18	ruby: restrict Address to being a type and not a variable name	Lena Olson
2013-06-09	ruby: stats: use gem5's stats for cache and memory controllers	Nilay Vaish
2013-05-21	ruby: add stats to .sm files, remove cache profiler	Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
2013-04-23	ruby: patch checkpoint restore with garnet	Nilay Vaish
2013-04-22	mem: Replace check with panic where inhibited should not happen	Andreas Hansson
2013-04-22	sim: separate nextCycle() and clockEdge() in clockedObjects	Dam Sunwoo