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Author
2012-09-11
Ruby: Use uint8_t instead of uint8 everywhere
Nilay Vaish
2012-09-10
Ruby System: Convert to Clocked Object
Nilay Vaish
2012-09-07
Param: Transition to Cycles for relevant parameters
Andreas Hansson
2012-09-05
Ruby Memory Controller: Fix clocking
Joel Hestness
2012-08-27
Ruby: Remove RubyEventQueue
Nilay Vaish
2012-08-27
Ruby Memory Vector: Allow more than 4GB of memory
Nilay Vaish
2012-08-22
Port: Extend the QueuedPort interface and use where appropriate
Andreas Hansson
2012-08-19
Ruby Banked Array: add copyrights
Nilay Vaish
2012-08-16
Ruby: Add RubySystem parameter to MemoryControl
Jason Power
2012-08-15
O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...
Anthony Gutierrez
2012-07-12
Ruby: remove config information from ruby.stats
Nilay Vaish
2012-07-11
ruby: improved DRAM reset comment
Brad Beckmann
2012-07-10
ruby: banked cache array resource model
Brad Beckmann
2012-07-10
ruby: tag and data cache access support
Joel Hestness
2012-07-10
ruby: adds reset function to Ruby memory controllers
Nuwan Jayasena
2012-07-10
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Nuwan Jayasena
2012-07-09
Port: Make getAddrRanges const
Andreas Hansson
2012-07-09
Port: Add isSnooping to slave port (asking master port)
Andreas Hansson
2012-05-22
Ruby Sequencer: Schedule deadlock check event at correct time
Nilay Vaish
2012-05-04
Ruby: Ensure snoop requests are sent using sendTimingSnoopReq
Andreas Hansson
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-25
Ruby: Remove extra statements from Sequencer
Nilay Vaish
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-04-14
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
Andreas Hansson
2012-04-12
Ruby: Ensure order-dependent iteration uses an ordered map
Andreas Hansson
2012-04-06
sim-ruby: checkpointing fixes and dependent eventq improvements
Brad Beckmann
2012-04-06
rubytest: seperated read and write ports.
Brad Beckmann
2012-04-06
MEM: Enable multiple distributed generalized memories
Andreas Hansson
2012-03-30
Ruby: Remove the physMemPort and instead access memory directly
Andreas Hansson
2012-03-30
MEM: Introduce the master/slave port sub-classes in C++
William Wang
2012-03-22
MEM: Split SimpleTimingPort into PacketQueue and ports
Andreas Hansson
2012-03-02
Ruby: Rename RubyPort::sendTiming to avoid overriding base class
Andreas Hansson
2012-02-24
MEM: Move port creation to the memory object(s) construction
Andreas Hansson
2012-02-13
MEM: Introduce the master/slave port roles in the Python classes
Andreas Hansson
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-02-10
Ruby: Remove isTagPresent() calls from Sequencer.cc
Nilay Vaish
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-30
MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
Andreas Hansson
2012-01-23
O3, Ruby: Forward invalidations from Ruby to O3 CPU
Nilay Vaish
2012-01-17
MEM: Remove the functional ports from the memory system
William Wang
2012-01-17
MEM: Separate queries for snooping and address ranges
Andreas Hansson
2012-01-17
MEM: Add port proxies instead of non-structural ports
Andreas Hansson
2012-01-12
PerfectCacheMemory: Remove references to CacheMsg
Nilay Vaish
2012-01-11
Ruby: Resurrect Cache Warmup Capability
Nilay Vaish
2012-01-11
Ruby Port: Add a list of cpu ports attached to this port
Nilay Vaish
2012-01-11
Ruby Sparse Memory: Add function for collating blocks
Nilay Vaish
2012-01-11
Ruby: Add infrastructure for recording cache contents
Nilay Vaish
2012-01-11
Ruby Memory Vector: Functions for collating and populating pages
Nilay Vaish
2012-01-10
Ruby: remove the files related to the tracer
Nilay Vaish
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