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path: root/src/mem/ruby/system
AgeCommit message (Expand)Author
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
2012-08-27Ruby Memory Vector: Allow more than 4GB of memoryNilay Vaish
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-08-19Ruby Banked Array: add copyrightsNilay Vaish
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-05-22Ruby Sequencer: Schedule deadlock check event at correct timeNilay Vaish
2012-05-04Ruby: Ensure snoop requests are sent using sendTimingSnoopReqAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-25Ruby: Remove extra statements from SequencerNilay Vaish
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
2012-04-06sim-ruby: checkpointing fixes and dependent eventq improvementsBrad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-02Ruby: Rename RubyPort::sendTiming to avoid overriding base classAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-10Ruby: Remove isTagPresent() calls from Sequencer.ccNilay Vaish
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-12PerfectCacheMemory: Remove references to CacheMsgNilay Vaish
2012-01-11Ruby: Resurrect Cache Warmup CapabilityNilay Vaish
2012-01-11Ruby Port: Add a list of cpu ports attached to this portNilay Vaish
2012-01-11Ruby Sparse Memory: Add function for collating blocksNilay Vaish
2012-01-11Ruby: Add infrastructure for recording cache contentsNilay Vaish
2012-01-11Ruby Memory Vector: Functions for collating and populating pagesNilay Vaish