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2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
2012-10-15ruby: improved support for functional accessesNilay Vaish
This patch adds support to different entities in the ruby memory system for more reliable functional read/write accesses. Only the simple network has been augmented as of now. Later on Garnet will also support functional accesses. The patch adds functional access code to all the different types of messages that protocols can send around. These messages are functionally accessed by going through the buffers maintained by the network entities. The patch also rectifies some of the bugs found in coherence protocols while testing the patch. With this patch applied, functional writes always succeed. But functional reads can still fail.
2012-10-15 ruby: register multiple memory controllersNilay Vaish
Currently the Ruby System maintains pointer to only one of the memory controllers. But there can be multiple controllers in the system. This patch adds a vector of memory controllers.
2012-10-15ruby: remove AbstractMemOrCacheNilay Vaish
The only place where this abstract class is in use is the memory controller, which it self is an abstract class. Does not seem useful at all.
2012-10-15ruby banked array: do away with event schedulingNilay Vaish
It seems unecessary that the BankedArray class needs to schedule an event to figure out when the access ends. Instead only the time for the end of access needs to be tracked.
2012-10-15ruby: reset timing after cache warm upNilay Vaish
Ruby system was recently converted to a clocked object. Such objects maintain state related to the time that has passed so far. During the cache warmup, Ruby system changes its own time and the global time. Later on, the global time is restored. So Ruby system also needs to reset its own time.
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
2012-10-02ruby: makes some members non-staticNilay Vaish
This patch makes some of the members (profiler, network, memory vector) of ruby system non-static.
2012-10-02ruby: changes to simple networkNilay Vaish
This patch makes the Switch structure inherit from BasicRouter, as is done in two other networks.
2012-10-02ruby: move functional access to ruby systemNilay Vaish
This patch moves the code for functional accesses to ruby system. This is because the subsequent patches add support for making functional accesses to the messages in the interconnect. Making those accesses from the ruby port would be cumbersome.
2012-09-23RubyPort and Sequencer: Fix drainingJoel Hestness
Fix the drain functionality of the RubyPort to only call drain on child ports during a system-wide drain process, instead of calling each time that a ruby_hit_callback is executed. This fixes the issue of the RubyPort ports being reawakened during the drain simulation, possibly with work they didn't previously have to complete. If they have new work, they may call process on the drain event that they had not registered work for, causing an assertion failure when completing the drain event. Also, in RubyPort, set the drainEvent to NULL when there are no events to be drained. If not set to NULL, the drain loop can result in stale drainEvents used.
2012-09-18ruby: eliminate typedef integer_tNilay Vaish
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish
This patch removes the use of g_system_ptr for event scheduling. Each consumer object now needs to specify upfront an EventManager object it would use for scheduling events. This makes the ruby memory system more amenable for a multi-threaded simulation.
2012-09-14scons: Use c++0x with gcc >= 4.4 instead of 4.6Andreas Hansson
This patch shifts the version of gcc for which we enable c++0x from 4.6 to 4.4 The more long term plan is to see what the c++0x features can bring and what level of support would be enabled simply by bumping the required version of gcc from 4.3 to 4.4. A few minor things had to be fixed in the code base, most notably the choice of a hashmap implementation. In the Ruby Sequencer there were also a few minor issues that gcc 4.4 was not too happy about.
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
This patch addresses a few minor issues reported by the clang static analyzer. The analysis was run with: scan-build -disable-checker deadcode \ -enable-checker experimental.core \ -disable-checker experimental.core.CastToStruct \ -enable-checker experimental.cpluscplus
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
This patch moves Ruby System from being a SimObject to recently introduced ClockedObject.
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
This patch is a first step to using Cycles as a parameter type. The main affected modules are the CPUs and the Ruby caches. There are definitely plenty more places that are affected, but this patch serves as a starting point to making the transition. An important part of this patch is to actually enable parameters to be specified as Param.Cycles which involves some changes to params.py.
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness
2012-08-28Ruby: Correct DataBlock =operatorJason Power
The =operator for the DataBlock class was incorrectly interpreting the class member m_alloc. This variable stands for whether the assigned memory for the data block needs to be freed or not by the class itself. It seems that the =operator interpreted the variable as whether the memory is assigned to the data block. This wrong interpretation was causing values not to propagate to RubySystem::m_mem_vec_ptr. This caused major issues with restoring from checkpoints when using a protocol which verified that the cache data was consistent with the backing store (i.e. MOESI-hammer).
2012-08-27Ruby: remove README.debugging and Decommissioning_noteNilay Vaish
These files were relevant when Ruby was part of GEMS. They are not required any longer.
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem or themselves for scheduling events.
2012-08-27Ruby Memory Vector: Allow more than 4GB of memoryNilay Vaish
The memory size variable was a 32-bit int. This meant that the size of the memory was limited to 4GB. This patch changes the type of the variable to 64-bit to support larger memory sizes. Thanks to Raghuraman Balasubramanian for bringing this to notice.
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
This patch extends the queued port interfaces with methods for scheduling the transmission of a timing request/response. The methods are named similar to the corresponding sendTiming(Snoop)Req/Resp, replacing the "send" with "sched". As the queues are currently unbounded, the methods always succeed and hence do not return a value. This functionality was previously provided in the subclasses by calling PacketQueue::schedSendTiming with the appropriate parameters. With this change, there is no need to introduce these extra methods in the subclasses, and the use of the queued interface is more uniform and explicit.
2012-08-19Ruby Banked Array: add copyrightsNilay Vaish
2012-08-16Ruby: Add RubySystem parameter to MemoryControlJason Power
This guarantees that RubySystem object is created before the MemoryController object is created.
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain ↵Anthony Gutierrez
DPRINTFs This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
2012-08-10Ruby: Clean up topology changesJason Power
This patch moves instantiateTopology into Ruby.py and removes the mem/ruby/network/topologies directory. It also adds some extra inheritance to the topologies to clean up some issues in the existing topologies.
2012-08-01Ruby NetDest: add assert for bad element in netdestJason Power
2012-07-12Ruby: remove config information from ruby.statsNilay Vaish
This patch removes printConfig() functions from all structures in Ruby. Most of the information is already part of config.ini, and where ever it is not, it would become in due course.
2012-07-12Ruby: remove some unused stuff from SLICC filesNilay Vaish
2012-07-11ruby: improved DRAM reset commentBrad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
ruby: fixed fatal print statement
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
ruby: fixed msgptr print call
2012-07-10ruby: banked cache array resource modelBrad Beckmann
This patch models a cache as separate tag and data arrays. The patch exposes the banked array as another resource that is checked by SLICC before a transition is allowed to execute. This is similar to how TBE entries and slots in output ports are modeled.
2012-07-10ruby: tag and data cache access supportJoel Hestness
Updates to Ruby to support statistics counting of cache accesses. This feature serves multiple purposes beyond simple stats collection. It provides the foundation for ruby to model the cache tag and data arrays as physical resources, as well as provide the necessary input data for McPAT power modeling.
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
Instead of just passing a list of controllers to the makeTopology function in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer which knows how to make the topology, possibly with some extra state set in the configs/ruby/<protocol>.py file. Thus, we can move all of the files from network/topologies to configs/topologies. A new class BaseTopology is added which all topologies in configs/topologies must inheirit from and follow its API. --HG-- rename : src/mem/ruby/network/topologies/Crossbar.py => configs/topologies/Crossbar.py rename : src/mem/ruby/network/topologies/Mesh.py => configs/topologies/Mesh.py rename : src/mem/ruby/network/topologies/MeshDirCorners.py => configs/topologies/MeshDirCorners.py rename : src/mem/ruby/network/topologies/Pt2Pt.py => configs/topologies/Pt2Pt.py rename : src/mem/ruby/network/topologies/Torus.py => configs/topologies/Torus.py
2012-07-09Port: Make getAddrRanges constAndreas Hansson
This patch makes getAddrRanges const throughout the code base. There is no reason why it should not be, and making it const prevents adding any unintentional side-effects.
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
This patch adds isSnooping to the slave port, and thus avoids going through getMasterPort to be able to ask the master. Over the course of the next few patches, all getMasterPort/getSlavePort in Port and MemObject are to be protocol agnostic, and the snooping is part of the protocol layer. The function is already present on the master port, where it is implemented by the module itself, e.g. a cache. On the slave side, it is merely asking the connected master port. The same name is used by both functions despite their difference in behaviour. The initial design used isMasterSnooping on the slave port side, but the more verbose function name was later changed.
2012-05-22Ruby: Remove the unused src/mem/ruby/common/Driver.* files.Nilay Vaish
2012-05-22Ruby Sequencer: Schedule deadlock check event at correct timeNilay Vaish
The scheduling of the deadlock check event was being done incorrectly as the clock was not being multiplied, so as to convert the time into ticks. This patch removes that bug.
2012-05-04Ruby: Ensure snoop requests are sent using sendTimingSnoopReqAndreas Hansson
This patch fixes a bug that caused snoop requests to be placed in a packet queue. Instead, the packet is now sent immediately using sendTimingSnoopReq, thus bypassing the packet queue and any normal responses waiting to be sent.
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
2012-04-28Garnet: Correct computation of link utilizationNilay Vaish
The computation for link utilization was incorrect for the flexible network. The utilization was being divided twice by the total time.
2012-04-25Ruby: Remove extra statements from SequencerNilay Vaish
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
This patch simplifies the packet by removing the broadcast flag and instead more firmly relying on (and enforcing) the semantics of transactions in the classic memory system, i.e. request packets are routed from a master to a slave based on the address, and when they are created they have neither a valid source, nor destination. On their way to the slave, the request packet is updated with a source field for all modules that multiplex packets from multiple master (e.g. a bus). When a request packet is turned into a response packet (at the final slave), it moves the potentially populated source field to the destination field, and the response packet is routed through any multiplexing components back to the master based on the destination field. Modules that connect multiplexing components, such as caches and bridges store any existing source and destination field in the sender state as a stack (just as before). The packet constructor is simplified in that there is no longer a need to pass the Packet::Broadcast as the destination (this was always the case for the classic memory system). In the case of Ruby, rather than using the parameter to the constructor we now rely on setDest, as there is already another three-argument constructor in the packet class. In many places where the packet information was printed as part of DPRINTFs, request packets would be printed with a numeric "dest" that would always be -1 (Broadcast) and that field is now removed from the printing.
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
This patch introduces port access methods that separates snoop request/responses from normal memory request/responses. The differentiation is made for functional, atomic and timing accesses and builds on the introduction of master and slave ports. Before the introduction of this patch, the packets belonging to the different phases of the protocol (request -> [forwarded snoop request -> snoop response]* -> response) all use the same port access functions, even though the snoop packets flow in the opposite direction to the normal packet. That is, a coherent master sends normal request and receives responses, but receives snoop requests and sends snoop responses (vice versa for the slave). These two distinct phases now use different access functions, as described below. Starting with the functional access, a master sends a request to a slave through sendFunctional, and the request packet is turned into a response before the call returns. In a system without cache coherence, this is all that is needed from the functional interface. For the cache-coherent scenario, a slave also sends snoop requests to coherent masters through sendFunctionalSnoop, with responses returned within the same packet pointer. This is currently used by the bus and caches, and the LSQ of the O3 CPU. The send/recvFunctional and send/recvFunctionalSnoop are moved from the Port super class to the appropriate subclass. Atomic accesses follow the same flow as functional accesses, with request being sent from master to slave through sendAtomic. In the case of cache-coherent ports, a slave can send snoop requests to a master through sendAtomicSnoop. Just as for the functional access methods, the atomic send and receive member functions are moved to the appropriate subclasses. The timing access methods are different from the functional and atomic in that requests and responses are separated in time and send/recvTiming are used for both directions. Hence, a master uses sendTiming to send a request to a slave, and a slave uses sendTiming to send a response back to a master, at a later point in time. Snoop requests and responses travel in the opposite direction, similar to what happens in functional and atomic accesses. With the introduction of this patch, it is possible to determine the direction of packets in the bus, and no longer necessary to look for both a master and a slave port with the requested port id. In contrast to the normal recvFunctional, recvAtomic and recvTiming that are pure virtual functions, the recvFunctionalSnoop, recvAtomicSnoop and recvTimingSnoop have a default implementation that calls panic. This is to allow non-coherent master and slave ports to not implement these functions.