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2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10# User Brad Beckmann <Brad.Beckmann@amd.com>Brad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
2012-07-10ruby: tag and data cache access supportJoel Hestness
2012-07-10ruby: adds reset function to Ruby memory controllersNuwan Jayasena
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-07-10ruby: changes how Topologies are createdBrad Beckmann
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-05-22Ruby: Remove the unused src/mem/ruby/common/Driver.* files.Nilay Vaish
2012-05-22Ruby Sequencer: Schedule deadlock check event at correct timeNilay Vaish
2012-05-04Ruby: Ensure snoop requests are sent using sendTimingSnoopReqAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-28Garnet: Correct computation of link utilizationNilay Vaish
2012-04-25Ruby: Remove extra statements from SequencerNilay Vaish
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
2012-04-06sim-ruby: checkpointing fixes and dependent eventq improvementsBrad Beckmann
2012-04-06rubytest: seperated read and write ports.Brad Beckmann
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30Ruby: Remove the physMemPort and instead access memory directlyAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-23Ruby: Fix Set::print for 32-bit hostsAndreas Hansson
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-22Scons: Remove Werror=False in SConscript filesAndreas Hansson
2012-03-19Garnet: Stats at vnet granularity + code cleanupTushar Krishna
2012-03-02Ruby: Rename RubyPort::sendTiming to avoid overriding base classAndreas Hansson
2012-02-24MEM: Move port creation to the memory object(s) constructionAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-10Ruby: Remove isTagPresent() calls from Sequencer.ccNilay Vaish
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-30MEM: Make the RubyPort physMemPort a PioPort instead of M5PortAndreas Hansson
2012-01-23O3, Ruby: Forward invalidations from Ruby to O3 CPUNilay Vaish
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-12PerfectCacheMemory: Remove references to CacheMsgNilay Vaish
2012-01-11Ruby: Resurrect Cache Warmup CapabilityNilay Vaish
2012-01-11Ruby Port: Add a list of cpu ports attached to this portNilay Vaish
2012-01-11Ruby EventQueue: Remove unused functionsNilay Vaish
2012-01-11Ruby Sparse Memory: Add function for collating blocksNilay Vaish
2012-01-11Ruby: Add infrastructure for recording cache contentsNilay Vaish
2012-01-11Ruby Memory Vector: Functions for collating and populating pagesNilay Vaish
2012-01-10Ruby: remove the files related to the tracerNilay Vaish
2012-01-10Sparse Memory: Simplify the structure for an entryNilay Vaish
2012-01-07Ruby Cache: Add param for marking caches as instruction onlyNilay Vaish
2012-01-06AbstractController: Remove some of the unused functionsNilay Vaish