gem5 - gem5

Age	Commit message (Collapse)	Author
2013-11-01	mem: Fixes for DRAM stats accounting	Andreas Hansson
	This patch fixes a number of stats accounting issues in the DRAM controller. Most importantly, it separates the system interface and DRAM interface so that it is clearer what the actual DRAM bandwidth (and consequently utilisation) is.
2013-11-01	mem: Adding stats for DRAM power calculation	Neha Agarwal
	This patch adds stats which are used for offline power calculation from the 'Micron Power Calculator' spreadsheet.
2013-11-01	mem: Unify request selection for read and write queues	Neha Agarwal
	This patch unifies the request selection across read and write queues for FR-FCFS scheduling policy. It also fixes the request selection code to prioritize the row hits present in the request queues over the selection based on earliest bank availability.
2013-11-01	mem: Add a simple adaptive version of the open-page policy	Andreas Hansson
	This patch adds a basic adaptive version of the open-page policy that guides the decision to keep open or close by looking at the contents of the controller queues. If no row hits are found, and bank conflicts are present, then the row is closed by means of an auto precharge. This is a well-known technique that should improve performance in most use-cases.
2013-11-01	mem: Just-in-time write scheduling in DRAM controller	Neha Agarwal
	This patch removes the untimed while loop in the write scheduling mechanism and now schedule commands taking into account the minimum timing constraint. It also introduces an optimization to track write queue size and switch from writes to reads if the number of write requests fall below write low threshold.
2013-11-01	mem: Add tRRD as a timing parameter for the DRAM controller	Andreas Hansson
	This patch adds the tRRD parameter to the DRAM controller. With the recent addition of the actAllowedAt member for each bank, this addition is trivial.
2013-11-01	mem: Make tXAW enforcement less conservative and per rank	Ani Udipi
	This patch changes the tXAW constraint so that it is enforced per rank rather than globally for all ranks in the channel. It also avoids using the bank freeAt to enforce the activation limit, as doing so also precludes performing any column or row command to the DRAM. Instead the patch introduces a new variable actAllowedAt for the banks and use this to track when a potential activation can occur.
2013-11-01	mem: Fix for 100% write threshold in DRAM controller	Neha Agarwal
	This patch fixes the controller when a write threshold of 100% is used. Earlier for 100% write threshold no data is written to memory as writes never get triggered since this corner case is not considered.
2013-11-01	mem: Pick the next DRAM request based on bank availability	Andreas Hansson
	This patch changes the FCFS bit of FR-FCFS such that requests that target the earliest available bank are picked first (as suggested in the original work on FR-FCFS by Rixner et al). To accommodate this we add functionality to identify a bank through a one-dimensional identifier (bank id). The member names of the DRAMPacket are also update to match the style guide.
2013-11-01	mem: Use the same timing calculation for DRAM read and write	Ani Udipi
	This patch simplifies the DRAM model by re-using the function that computes the busy and access time for both reads and writes.
2013-11-01	mem: Fix DRAM bank occupancy for streaming access	Ani Udipi
	This patch fixes an issue that allowed more than 100% bus utilisation in certain cases.
2013-11-01	mem: Schedule time for DRAM event taking tRAS into account	Ani Udipi
	This patch changes the time the controller is woken up to take the next scheduling decisions. tRAS is now handled in estimateLatency and doDRAMAccess and we do not need to worry about it at scheduling time. The earliest we need to wake up is to do a pre-charge, row access and column access before the bus becomes free for use.
2013-11-01	mem: Add tRAS parameter to the DRAM controller model	Ani Udipi
	This patch adds an explicit tRAS parameter to the DRAM controller model. Previously tRAS was, rather conservatively, assumed to be tRCD + tCL + tRP. The default values for tRAS are chosen to match the previous behaviour and will be updated later.
2013-08-19	stats: Cumulative stats update	Andreas Hansson
	This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
2013-08-19	mem: Use STL deque in favour of list for DRAM queues	Andreas Hansson
	This patch changes the data structure used for the DRAM read, write and response queues from an STL list to deque. This optimisation is based on the observation that the size is small (and fixed), and that the structures are frequently iterated over in a linear fashion.
2013-08-19	mem: Perform write merging in the DRAM write queue	Andreas Hansson
	This patch implements basic write merging in the DRAM to avoid redundant bursts. When a new access is added to the queue it is compared against the existing entries, and if it is either intersecting or immediately succeeding/preceeding an existing item it is merged. There is currently no attempt made at avoiding iterating over the existing items in determining whether merging is possible or not.
2013-08-19	mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM	Amin Farmahini
	This patch gets rid of bytesPerCacheLine parameter and makes the DRAM configuration separate from cache line size. Instead of bytesPerCacheLine, we define a parameter for the DRAM called burst_length. The burst_length parameter shows the length of a DRAM device burst in bits. Also, lines_per_rowbuffer is replaced with device_rowbuffer_size to improve code portablity. This patch adds a burst length in beats for each memory type, an interface width for each memory type, and the memory controller model is extended to reason about "system" packets vs "dram" packets and assemble the responses properly. It means that system packets larger than a full burst are split into multiple dram packets.
2013-08-19	mem: Warn instead of panic for tXAW violation	Andreas Hansson
	Until the performance bug is fixed, avoid killing simulations.
2013-08-19	mem: Allow disabling of tXAW through a 0 activation limit	Andreas Hansson
	This patch fixes an issue where an activation limit of 0 was not allowed. With this patch, setting the limit to 0 simply disables the tXAW constraint.
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
	This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly.
2013-05-30	mem: Add bytes per activate DRAM controller stat	Andreas Hansson
	This patch adds a histogram to track how many bytes are accessed in an open row before it is closed. This metric is useful in characterising a workload and the efficiency of the DRAM scheduler. For example, a DDR3-1600 device requires 44 cycles (tRC) before it can activate another row in the same bank. For a x32 interface (8 bytes per cycle) that means 8 x 44 = 352 bytes must be transferred to hide the preparation time.
2013-05-30	mem: Add static latency to the DRAM controller	Andreas Hansson
	This patch adds a frontend and backend static latency to the DRAM controller by delaying the responses. Two parameters expressing the frontend and backend contributions in absolute time are added to the controller, and the appropriate latency is added to the responses when adding them to the (infinite) queued port for sending. For writes and reads that hit in the write buffer, only the frontend latency is added. For reads that are serviced by the DRAM, the static latency is the sum of the pipeline latencies of the entire frontend, backend and PHY. The default values are chosen based on having roughly 10 pipeline stages in total at 500 MHz. In the future, it would be sensible to make the controller use its clock and convert these latencies (and a few of the DRAM timings) to cycles.
2013-04-22	mem: Address mapping with fine-grained channel interleaving	Andreas Hansson
	This patch adds an address mapping scheme where the channel interleaving takes place on a cache line granularity. It is similar to the existing RaBaChCo that interleaves on a DRAM page, but should give higher performance when there is less locality in the address stream.
2013-04-22	mem: More descriptive enum names for address mapping	Andreas Hansson
	This patch changes the slightly ambigious names used for the address mapping scheme to be more descriptive, and actually spell out what they do. With this patch we also open up for adding more flavours of open- and close-type mappings, i.e. interleaving across channels with the open map.
2013-03-18	mem: Fix missing delete of packet in DRAM access	Andreas Hansson
	This patch fixes a memory leak caused by not deleting packets that require no response.
2013-03-01	mem: Add check if SimpleDRAM nextReqEvent is scheduled	Andreas Hansson
	This check covers a case where a retry is called from the SimpleDRAM causing a new request to appear before the DRAM itself schedules a nextReqEvent. By adding this check, the event is not scheduled twice.
2013-03-01	mem: SimpleDRAM variable naming and whitespace fixes	Andreas Hansson
	This patch fixes a number of small cosmetic issues in the SimpleDRAM module. The most important change is to move the accounting of received packets to after the check is made if the packet should be retried or not. Thus, packets are only counted if they are actually accepted.
2013-03-01	mem: Add support for multi-channel DRAM configurations	Andreas Hansson
	This patch adds support for multi-channel instances of the DRAM controller model by stripping away the channel bits in the address decoding. The patch relies on the availiability of address interleaving and, at this time, it is up to the user to configure the interleaving appropriately. At the moment it is assumed that the channel interleaving bits are immediately following the column bits (smallest sensible interleaving). Convenience methods for building multi-channel configurations will be added later.
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
	This patch adds a check to ensure that the delay incurred by the bus is not simply disregarded, but accounted for by someone. At this point, all the modules do is to zero it out, and no additional time is spent. This highlights where the bus timing is simply dropped instead of being paid for. As a follow up, the locations identified in this patch should add this additional time to the packets in one way or another. For now it simply acts as a sanity check and highlights where the delay is simply ignored. Since no time is added, all regressions remain the same.
2013-01-31	mem: Add comments for the DRAM address decoding	Andreas Hansson
	This patch adds more verbose comments to explain the two different address mapping schemes of the DRAM controller.
2013-01-31	mem: Add tTAW and tFAW to the SimpleDRAM model	Ani Udipi
	This patch adds two additional scheduling constraints to the DRAM controller model, to constrain the activation rate. The two metrics are determine the size of the activation window in terms of the number of activates and the minimum time required for that number of activates. This maps to current DDRx, LPDDRx and WIOx standards that have either tFAW (4 activate window) or tTAW (2 activate window) scheduling constraints.
2013-01-31	mem: Separate out the different cases for DRAM bus busy time	Andreas Hansson
	This patch changes how the data bus busy time is calculated such that it is delayed to the actual scheduling time of the request as opposed to being done as soon as possible. This patch changes a bunch of statistics, and the stats update is bundled together with the introruction of tFAW/tTAW and the named DRAM configurations like DDR3 and LPDDR2.
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
	This patch adds a _curTick variable to an eventq. This variable is updated whenever an event is serviced in function serviceOne(), or all events upto a particular time are processed in function serviceEvents(). This change helps when there are eventqs that do not make use of curTick for scheduling events.
2012-11-08	mem: Fix DRAM draining to ensure write queue is empty	Andreas Hansson
	This patch fixes the draining of the SimpleDRAM controller model. The controller performs buffering of writes and normally there is no need to ever empty the write buffer (if you have a fast on-chip memory, then use it). The patch adds checks to ensure the write buffer is drained when the controller is asked to do so.
2012-11-02	mem: fix use after free issue in memories until 4-phase work complete.	Ali Saidi

2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
	This patch moves the draining interface from SimObject to a separate class that can be used by any object needing draining. However, objects not visible to the Python code (i.e., objects not deriving from SimObject) still depend on their parents informing them when to drain. This patch also gets rid of the CountedDrainEvent (which isn't really an event) and replaces it with a DrainManager.
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
	This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default.
2012-09-21	DRAM: Introduce SimpleDRAM to capture a high-level controller	Andreas Hansson
	This patch introduces a high-level model of a DRAM controller, with a basic read/write buffer structure, a selectable and customisable arbiter, a few address mapping options, and the basic DRAM timing constraints. The parameters make it possible to turn this model into any desired DDRx/LPDDRx/WideIOx memory controller. The intention is not to be cycle accurate or capture every aspect of a DDR DRAM interface, but rather to enable exploring of the high-level knobs with a good simulation speed. Thus, contrary to e.g. DRAMSim this module emphasizes simulation speed with a good-enough accuracy. This module is merely a starting point, and there are plenty additions and improvements to come. A notable addition is the support for address-striping in the bus to enable a multi-channel DRAM controller. Also note that there are still a few "todo's" in the code base that will be addressed as we go along. A follow-up patch will add basic performance regressions that use the traffic generator to exercise a few well-defined corner cases.