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path: root/src/mem/simple_dram.cc
AgeCommit message (Expand)Author
2013-05-30mem: Add bytes per activate DRAM controller statAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-04-22mem: Address mapping with fine-grained channel interleavingAndreas Hansson
2013-04-22mem: More descriptive enum names for address mappingAndreas Hansson
2013-03-18mem: Fix missing delete of packet in DRAM accessAndreas Hansson
2013-03-01mem: Add check if SimpleDRAM nextReqEvent is scheduledAndreas Hansson
2013-03-01mem: SimpleDRAM variable naming and whitespace fixesAndreas Hansson
2013-03-01mem: Add support for multi-channel DRAM configurationsAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-01-31mem: Add comments for the DRAM address decodingAndreas Hansson
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
2013-01-31mem: Separate out the different cases for DRAM bus busy timeAndreas Hansson
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-08mem: Fix DRAM draining to ensure write queue is emptyAndreas Hansson
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson