gem5 - gem5

Age	Commit message (Expand)	Author
2013-08-19	stats: Cumulative stats update	Andreas Hansson
2013-08-19	mem: Use STL deque in favour of list for DRAM queues	Andreas Hansson
2013-08-19	mem: Perform write merging in the DRAM write queue	Andreas Hansson
2013-08-19	mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM	Amin Farmahini
2013-08-19	mem: Warn instead of panic for tXAW violation	Andreas Hansson
2013-08-19	mem: Allow disabling of tXAW through a 0 activation limit	Andreas Hansson
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-05-30	mem: Add bytes per activate DRAM controller stat	Andreas Hansson
2013-05-30	mem: Add static latency to the DRAM controller	Andreas Hansson
2013-04-22	mem: Address mapping with fine-grained channel interleaving	Andreas Hansson
2013-04-22	mem: More descriptive enum names for address mapping	Andreas Hansson
2013-03-18	mem: Fix missing delete of packet in DRAM access	Andreas Hansson
2013-03-01	mem: Add check if SimpleDRAM nextReqEvent is scheduled	Andreas Hansson
2013-03-01	mem: SimpleDRAM variable naming and whitespace fixes	Andreas Hansson
2013-03-01	mem: Add support for multi-channel DRAM configurations	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-01-31	mem: Add comments for the DRAM address decoding	Andreas Hansson
2013-01-31	mem: Add tTAW and tFAW to the SimpleDRAM model	Ani Udipi
2013-01-31	mem: Separate out the different cases for DRAM bus busy time	Andreas Hansson
2012-11-16	sim: have a curTick per eventq	Nilay Vaish
2012-11-08	mem: Fix DRAM draining to ensure write queue is empty	Andreas Hansson
2012-11-02	mem: fix use after free issue in memories until 4-phase work complete.	Ali Saidi
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-09-21	DRAM: Introduce SimpleDRAM to capture a high-level controller	Andreas Hansson