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simple_dram.hh
Age
Commit message (
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Author
2013-11-01
mem: Adding stats for DRAM power calculation
Neha Agarwal
2013-11-01
mem: Unify request selection for read and write queues
Neha Agarwal
2013-11-01
mem: Just-in-time write scheduling in DRAM controller
Neha Agarwal
2013-11-01
mem: Add tRRD as a timing parameter for the DRAM controller
Andreas Hansson
2013-11-01
mem: Make tXAW enforcement less conservative and per rank
Ani Udipi
2013-11-01
mem: Pick the next DRAM request based on bank availability
Andreas Hansson
2013-11-01
mem: Use the same timing calculation for DRAM read and write
Ani Udipi
2013-11-01
mem: Add tRAS parameter to the DRAM controller model
Ani Udipi
2013-08-19
mem: Use STL deque in favour of list for DRAM queues
Andreas Hansson
2013-08-19
mem: Perform write merging in the DRAM write queue
Andreas Hansson
2013-08-19
mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAM
Amin Farmahini
2013-05-30
mem: Add bytes per activate DRAM controller stat
Andreas Hansson
2013-05-30
mem: Add static latency to the DRAM controller
Andreas Hansson
2013-03-01
mem: SimpleDRAM variable naming and whitespace fixes
Andreas Hansson
2013-03-01
mem: Add support for multi-channel DRAM configurations
Andreas Hansson
2013-01-31
mem: Add tTAW and tFAW to the SimpleDRAM model
Ani Udipi
2012-11-02
mem: fix use after free issue in memories until 4-phase work complete.
Ali Saidi
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-10-15
Port: Add protocol-agnostic ports in the port hierarchy
Andreas Hansson
2012-09-21
DRAM: Introduce SimpleDRAM to capture a high-level controller
Andreas Hansson