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path: root/src/mem/simple_dram.hh
AgeCommit message (Expand)Author
2013-08-19mem: Use STL deque in favour of list for DRAM queuesAndreas Hansson
2013-08-19mem: Perform write merging in the DRAM write queueAndreas Hansson
2013-08-19mem: Replacing bytesPerCacheLine with DRAM burstLength in SimpleDRAMAmin Farmahini
2013-05-30mem: Add bytes per activate DRAM controller statAndreas Hansson
2013-05-30mem: Add static latency to the DRAM controllerAndreas Hansson
2013-03-01mem: SimpleDRAM variable naming and whitespace fixesAndreas Hansson
2013-03-01mem: Add support for multi-channel DRAM configurationsAndreas Hansson
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson