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path: root/src/mem/simple_mem.cc
AgeCommit message (Expand)Author
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-16mem: Dynamically determine page bytes in memory componentsAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-19mem: Check return value of checkFunctional in SimpleMemoryAndreas Hansson
2013-09-18mem: Fix scheduling bug in SimpleMemoryAndreas Hansson
2013-08-19mem: Add an internal packet queue in SimpleMemoryAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-01-08mem: Fix use-after-free bugMitch Hayenga
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-09-18Mem: Add a maximum bandwidth to SimpleMemoryAndreas Hansson
2012-07-12Mem: Make SimpleMemory single portedAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
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