gem5 - gem5

Age	Commit message (Expand)	Author
2015-12-31	mem: Make cache terminology easier to understand	Andreas Hansson
2015-11-06	mem: Use the packet delays and do not just zero them out	Andreas Hansson
2015-11-06	mem: Align rules for sinking inhibited packets at the slave	Andreas Hansson
2015-11-06	mem: Unify delayed packet deletion	Andreas Hansson
2015-07-13	mem: Fix (ab)use of emplace to avoid temporary object creation	Andreas Hansson
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-03-19	mem: Use emplace front/back for deferred packets	Andreas Hansson
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-11	mem: Clarification of packet crossbar timings	Marco Balboni
2014-10-29	arm, mem: Fix drain bug and provide drain prints for more components.	Ali Saidi
2014-10-16	mem: Dynamically determine page bytes in memory components	Andreas Hansson
2014-09-20	mem: Rename Bus to XBar to better reflect its behaviour	Andreas Hansson
2014-09-19	mem: Check return value of checkFunctional in SimpleMemory	Andreas Hansson
2013-09-18	mem: Fix scheduling bug in SimpleMemory	Andreas Hansson
2013-08-19	mem: Add an internal packet queue in SimpleMemory	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-01-08	mem: Fix use-after-free bug	Mitch Hayenga
2012-11-02	mem: fix use after free issue in memories until 4-phase work complete.	Ali Saidi
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-09-18	Mem: Add a maximum bandwidth to SimpleMemory	Andreas Hansson
2012-07-12	Mem: Make SimpleMemory single ported	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson