gem5 - gem5

Age	Commit message (Collapse)	Author
2010-08-20	ruby: Stall and wait input messages instead of recycling	Brad Beckmann
	This patch allows messages to be stalled in their input buffers and wait until a corresponding address changes state. In order to make this work, all in_ports must be ranked in order of dependence and those in_ports that may unblock an address, must wake up the stalled messages. Alot of this complexity is handled in slicc and the specification files simply annotate the in_ports. --HG-- rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/StallAndWaitStatementAST.py rename : src/mem/slicc/ast/CheckAllocateStatementAST.py => src/mem/slicc/ast/WakeUpDependentsStatementAST.py
2010-04-02	ruby: get "using namespace" out of headers	Nathan Binkert
	In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates.
2010-03-10	slicc: have a central mechanism for creating a code_formatter.	Nathan Binkert
	This makes it easier to add global variables like protocol
2010-01-29	ruby: Allows boolean and string defaults for StateMachine parameters	Brad Beckmann

2010-01-29	ruby: Ruby changes required to use the python config system	Brad Beckmann
	This patch includes the necessary changes to connect ruby objects using the python configuration system. Mainly it consists of removing unnecessary ruby object pointers and connecting the necessary object pointers using the generated param objects. This patch includes the slicc changes necessary to connect generated ruby objects together using the python configuraiton system.
2010-01-29	ruby: Make SLICC-generated objects SimObjects.	Steve Reinhardt
	Also add SLICC support for state-machine parameter defaults (passed through to Python as SimObject Param defaults).
2010-01-19	ruby: new atomics implementation	Derek Hower
	This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
2009-11-05	slicc: tweak file enumeration for scons	Steve Reinhardt
	Right now .cc and .hh files are handled separately, but then they're just munged together at the end by scons, so it doesn't buy us anything. Might as well munge from the start since we'll eventually be adding generated Python files to the list too.
2009-09-22	slicc: Pure python implementation of slicc.	Nathan Binkert
	This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc