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2015-07-20slicc: support for multiple cache entry types in the same state machineDavid Hashe
To have multiple Entry types (e.g., a cache Entry type and a directory Entry type), just declare one of them as a secondary type by using the pair 'main="false"', e.g.: structure(DirEntry, desc="...", interface="AbstractCacheEntry", main="false") { ...and the primary type would be declared: structure(Entry, desc="...", interface="AbstractCacheEntry") {
2015-07-20slicc: Fix bug in enqueue and peek statements.David Hashe
These were not generating the correct c names for types declared within a machine scope.
2015-07-20slicc: fix missing inline function in LocalVariableASTDavid Hashe
2015-07-20slicc: improve support for prefix operationsDavid Hashe
This patch fixes the type handling when prefix operations are used. Previously prefix operators would assume a void return type, which made it impossible to combine prefix operations with other expressions. This patch allows SLICC programmers to use prefix operations more naturally.
2015-07-20slicc: support for transitions with a wildcard next stateDavid Hashe
This patches adds support for transitions of the form: transition(START, EVENTS, *) { ACTIONS } This allows a machine to collapse states that differ only in the next state transition to collapse into one, and can help shorten/simplfy some protocols significantly. When * is encountered as an end state of a transition, the next state is determined by calling the machine-specific getNextState function. The next state is determined before any actions of the transition execute, and therefore the next state calculation cannot depend on any of the transition actions.
2015-07-20slicc: support for multiple message types on the same bufferDavid Hashe
This patch allows SLICC protocols to use more than one message type with a message buffer. For example, you can declare two in ports as such: in_port(ResponseQueue_in, ResponseMsg, responseFromDir, rank=3) { ... } in_port(tgtResponseQueue_in, TgtResponseMsg, responseFromDir, rank=2) { ... }
2015-08-01slicc: fatal->panic on invalid transitionsBrad Beckmann
2015-07-20slicc: isinstance bugfixDavid Hashe
This fix prevents spurious errors when searching for a symbol that may be located in one of multiple symbol tables.
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
This is another step in the process of removing global variables from Ruby to enable multiple RubySystem instances in a single simulation. The list of abstract controllers is per-RubySystem and should be represented that way, rather than as a global. Since this is the last remaining Ruby global variable, the src/mem/ruby/Common/Global.* files are also removed.
2015-07-10ruby: replace global g_system_ptr with per-object pointersBrandon Potter
This is another step in the process of removing global variables from Ruby to enable multiple RubySystem instances in a single simulation. With possibly multiple RubySystem objects, we can no longer use a global variable to find "the" RubySystem object. Instead, each Ruby component has to carry a pointer to the RubySystem object to which it belongs.
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-04ruby: drop NetworkMessage classNilay Vaish
This patch drops the NetworkMessage class. The relevant data members and functions have been moved to the Message class, which was the parent of NetworkMessage.
2015-06-25ruby: slicc: remove READMENilay Vaish
No longer maintained. Updates are only made to the wiki page. So being dropped.
2014-11-06ruby: interface with classic memory controllerNilay Vaish
This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.
2014-11-06ruby: remove the function functionalReadBuffers()Nilay Vaish
This function was added when I had incorrectly arrived at the conclusion that such a function can improve the chances of a functional read succeeding. As was later realized, this is not possible in the current setup. While the code using this function was dropped long back, this function was not. Hence the patch.
2014-11-06ruby: slicc: allow adding a bool to an int, like C++.Nilay Vaish
2014-10-16mem: Use shared_ptr for Ruby Message classesAndreas Hansson
This patch transitions the Ruby Message and its derived classes from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly replacing "new" with "make_shared". The cloning of derived messages is slightly changed as they previously relied on overriding the base-class through covariant return types.
2014-09-01ruby: message buffers: significant changesNilay Vaish
This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work.
2014-09-01ruby: slicc: change the way configurable members are specifiedNilay Vaish
There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='.
2014-09-01ruby: slicc: improve the grammarNilay Vaish
This patch changes the grammar for SLICC so as to remove some of the redundant / duplicate rules. In particular rules for object/variable declaration and class member declaration have been unified. Similarly, the rules for a general function and a class method have been unified. One more change is in the priority of two rules. The first rule is on declaring a function with all the params typed and named. The second rule is on declaring a function with all the params only typed. Earlier the second rule had a higher priority. Now the first rule has a higher priority.
2014-09-01ruby: slicc: donot prefix machine name to variablesNilay Vaish
This changeset does away with prefixing of member variables of state machines with the identity of the machine itself.
2014-09-01ruby: remove unused toString() from AbstractControllerNilay Vaish
2014-09-01ruby: move files from ruby/system to ruby/structuresNilay Vaish
The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array. The directory ruby/systems has the glue code that holds these structures together. --HG-- rename : src/mem/ruby/system/MachineID.hh => src/mem/ruby/common/MachineID.hh rename : src/mem/ruby/buffers/MessageBuffer.cc => src/mem/ruby/network/MessageBuffer.cc rename : src/mem/ruby/buffers/MessageBuffer.hh => src/mem/ruby/network/MessageBuffer.hh rename : src/mem/ruby/buffers/MessageBufferNode.cc => src/mem/ruby/network/MessageBufferNode.cc rename : src/mem/ruby/buffers/MessageBufferNode.hh => src/mem/ruby/network/MessageBufferNode.hh rename : src/mem/ruby/system/AbstractReplacementPolicy.hh => src/mem/ruby/structures/AbstractReplacementPolicy.hh rename : src/mem/ruby/system/BankedArray.cc => src/mem/ruby/structures/BankedArray.cc rename : src/mem/ruby/system/BankedArray.hh => src/mem/ruby/structures/BankedArray.hh rename : src/mem/ruby/system/Cache.py => src/mem/ruby/structures/Cache.py rename : src/mem/ruby/system/CacheMemory.cc => src/mem/ruby/structures/CacheMemory.cc rename : src/mem/ruby/system/CacheMemory.hh => src/mem/ruby/structures/CacheMemory.hh rename : src/mem/ruby/system/DirectoryMemory.cc => src/mem/ruby/structures/DirectoryMemory.cc rename : src/mem/ruby/system/DirectoryMemory.hh => src/mem/ruby/structures/DirectoryMemory.hh rename : src/mem/ruby/system/DirectoryMemory.py => src/mem/ruby/structures/DirectoryMemory.py rename : src/mem/ruby/system/LRUPolicy.hh => src/mem/ruby/structures/LRUPolicy.hh rename : src/mem/ruby/system/MemoryControl.cc => src/mem/ruby/structures/MemoryControl.cc rename : src/mem/ruby/system/MemoryControl.hh => src/mem/ruby/structures/MemoryControl.hh rename : src/mem/ruby/system/MemoryControl.py => src/mem/ruby/structures/MemoryControl.py rename : src/mem/ruby/system/MemoryNode.cc => src/mem/ruby/structures/MemoryNode.cc rename : src/mem/ruby/system/MemoryNode.hh => src/mem/ruby/structures/MemoryNode.hh rename : src/mem/ruby/system/MemoryVector.hh => src/mem/ruby/structures/MemoryVector.hh rename : src/mem/ruby/system/PerfectCacheMemory.hh => src/mem/ruby/structures/PerfectCacheMemory.hh rename : src/mem/ruby/system/PersistentTable.cc => src/mem/ruby/structures/PersistentTable.cc rename : src/mem/ruby/system/PersistentTable.hh => src/mem/ruby/structures/PersistentTable.hh rename : src/mem/ruby/system/PseudoLRUPolicy.hh => src/mem/ruby/structures/PseudoLRUPolicy.hh rename : src/mem/ruby/system/RubyMemoryControl.cc => src/mem/ruby/structures/RubyMemoryControl.cc rename : src/mem/ruby/system/RubyMemoryControl.hh => src/mem/ruby/structures/RubyMemoryControl.hh rename : src/mem/ruby/system/RubyMemoryControl.py => src/mem/ruby/structures/RubyMemoryControl.py rename : src/mem/ruby/system/SparseMemory.cc => src/mem/ruby/structures/SparseMemory.cc rename : src/mem/ruby/system/SparseMemory.hh => src/mem/ruby/structures/SparseMemory.hh rename : src/mem/ruby/system/TBETable.hh => src/mem/ruby/structures/TBETable.hh rename : src/mem/ruby/system/TimerTable.cc => src/mem/ruby/structures/TimerTable.cc rename : src/mem/ruby/system/TimerTable.hh => src/mem/ruby/structures/TimerTable.hh rename : src/mem/ruby/system/WireBuffer.cc => src/mem/ruby/structures/WireBuffer.cc rename : src/mem/ruby/system/WireBuffer.hh => src/mem/ruby/structures/WireBuffer.hh rename : src/mem/ruby/system/WireBuffer.py => src/mem/ruby/structures/WireBuffer.py rename : src/mem/ruby/recorder/CacheRecorder.cc => src/mem/ruby/system/CacheRecorder.cc rename : src/mem/ruby/recorder/CacheRecorder.hh => src/mem/ruby/system/CacheRecorder.hh
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'. It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up. Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code.
2014-05-23ruby: slicc: remove unused ids DNUCA*Nilay Vaish
2014-05-23ruby: message buffer: drop dequeue_getDelayCycles()Nilay Vaish
The functionality of updating and returning the delay cycles would now be performed by the dequeue() function itself.
2014-04-19ruby: slicc: remove old documentationNilay Vaish
Has not been maintained at all. Since there is alternate documentation available on gem5.org, no need to have this separately.
2014-04-19ruby: slicc: slight change to rule for transitionsNilay Vaish
It had an unnecessary pairs token which is being removed.
2014-04-08ruby: slicc: change enqueue statementNilay Vaish
As of now, the enqueue statement can take in any number of 'pairs' as argument. But we only use the pair in which latency is the key. This latency is allowed to be either a fixed integer or a member variable of controller in which the expression appears. This patch drops the use of pairs in an enqueue statement. Instead, an expression is allowed which will be interpreted to be the latency of the enqueue. This expression can anything allowed by slicc including a constant integer or a member variable.
2014-03-20ruby: slicc: code refactorNilay Vaish
2014-02-23ruby: slicc: remove unused COPY_HEAD functionalityNilay Vaish
2014-02-20ruby: controller: slight code refactoringNilay Vaish
2014-02-20ruby: slicc: slight code refactoringNilay Vaish
2014-01-10ruby: move all statistics to stats.txt, eliminate ruby.statsNilay Vaish
2014-01-09ruby: fix bug introduced to revision 8523754f8885Nilay Vaish
2014-01-08ruby: slicc: remove variable 'addr' used in calls to doTransitionNilay Vaish
This variable causes trouble if a variable of same name is declared in a protocol file. Hence it is being eliminated.
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers.
2014-01-04ruby: add support for clustersNilay Vaish
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
This patch replaces max_in_port_rank with the number of inports. The use of max_in_port_rank was causing spurious re-builds and incorrect initialization of variables in ruby related regression tests. This was due to the variable value being used across threads while compiling when it was not meant to be. Since the number of inports is state machine specific value, this problem should get solved.
2013-09-06ruby: converts sparse memory stats to gem5 styleNilay Vaish
2013-08-07ruby: slicc: remove double trigger, continueProcessingNilay Vaish
These constructs are not in use and are not being maintained by any one. In addition, it is not known if doubleTrigger works correctly with Ruby now.
2013-08-07ruby: slicc: move some code to AbstractControllerNilay Vaish
Some of the code in StateMachine.py file is added to all the controllers and is independent of the controller definition. This code is being moved to the AbstractController class which is the parent class of all controllers.
2013-07-11ruby: removed the very old double trigger hackBrad Beckmann
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-28ruby: append transition comment only when in opt/debugNilay Vaish
2013-06-25ruby: profiler: lots of inter-related changesNilay Vaish
The patch started of with removing the global variables from the profiler for profiling the miss latency of requests made to the cache. The corrresponding histograms have been moved to the Sequencer. These are combined together when the histograms are printed. Separate histograms are now maintained for tracking latency of all requests together, of hits only and of misses only. A particular set of histograms used to use the type GenericMachineType defined in one of the protocol files. This patch removes this type. Now, everything that relied on this type would use MachineType instead. To do this, SLICC has been changed so that multiple machine types can be declared by a controller in its preamble.
2013-06-18ruby: fix slicc compiler to complain about duplicate symbolsLena Olson
Previously, .sm files were allowed to use the same name for a type and a variable. This is unnecessarily confusing and has some bad side effects, like not being able to declare later variables in the same scope with the same type. This causes the compiler to complain and die on things like Address Address. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-09ruby: stats: use gem5's stats for cache and memory controllersNilay Vaish
This moves event and transition count statistics for cache controllers to gem5's statistics. It does the same for the statistics associated with the memory controller in ruby. All the cache/directory/dma controllers individually collect the event and transition counts. A callback function, collateStats(), has been added that is invoked on the controller version 0 of each controller class. This function adds all the individual controller statistics to a vector variables. All the code for registering the statistical variables and collating them is generated by SLICC. The patch removes the files *_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for collecting and dumping statistics respectively.
2013-05-21ruby: slicc: fix error msg in TypeFieldMemberAST.pyMalek Musleh
2013-05-21ruby: add stats to .sm files, remove cache profilerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
This patch changes the way cache statistics are collected in ruby. As of now, there is separate entity called CacheProfiler which holds statistical variables for caches. The CacheMemory class defines different functions for accessing the CacheProfiler. These functions are then invoked in the .sm files. I find this approach opaque and prone to error. Secondly, we probably should not be paying the cost of a function call for recording statistics. Instead, this patch allows for accessing statistical variables in the .sm files. The collection would become transparent. Secondly, it would happen in place, so no function calls. The patch also removes the CacheProfiler class. --HG-- rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py
2013-04-09Ruby: Add field to slicc machine for generic typeJoel Hestness
This allows you to have (i.e.) an L2 cache that is not named "L2Cache" but is still a GenericMachineType_L2Cache. This is particularly helpful if the protocol has multiple L2 controllers.