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2014-01-09ruby: fix bug introduced to revision 8523754f8885Nilay Vaish
2014-01-08ruby: slicc: remove variable 'addr' used in calls to doTransitionNilay Vaish
This variable causes trouble if a variable of same name is declared in a protocol file. Hence it is being eliminated.
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
The first two levels (L0, L1) are private to the core, the third level (L2)is possibly shared. The protocol supports clustered designs. For example, one can have two sets of two cores. Each core has an L0 and L1 cache. There are two L2 controllers where each set accesses only one of the L2 controllers.
2014-01-04ruby: add support for clustersNilay Vaish
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
This patch replaces max_in_port_rank with the number of inports. The use of max_in_port_rank was causing spurious re-builds and incorrect initialization of variables in ruby related regression tests. This was due to the variable value being used across threads while compiling when it was not meant to be. Since the number of inports is state machine specific value, this problem should get solved.
2013-09-06ruby: converts sparse memory stats to gem5 styleNilay Vaish
2013-08-07ruby: slicc: remove double trigger, continueProcessingNilay Vaish
These constructs are not in use and are not being maintained by any one. In addition, it is not known if doubleTrigger works correctly with Ruby now.
2013-08-07ruby: slicc: move some code to AbstractControllerNilay Vaish
Some of the code in StateMachine.py file is added to all the controllers and is independent of the controller definition. This code is being moved to the AbstractController class which is the parent class of all controllers.
2013-07-11ruby: removed the very old double trigger hackBrad Beckmann
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-28ruby: append transition comment only when in opt/debugNilay Vaish
2013-06-25ruby: profiler: lots of inter-related changesNilay Vaish
The patch started of with removing the global variables from the profiler for profiling the miss latency of requests made to the cache. The corrresponding histograms have been moved to the Sequencer. These are combined together when the histograms are printed. Separate histograms are now maintained for tracking latency of all requests together, of hits only and of misses only. A particular set of histograms used to use the type GenericMachineType defined in one of the protocol files. This patch removes this type. Now, everything that relied on this type would use MachineType instead. To do this, SLICC has been changed so that multiple machine types can be declared by a controller in its preamble.
2013-06-18ruby: fix slicc compiler to complain about duplicate symbolsLena Olson
Previously, .sm files were allowed to use the same name for a type and a variable. This is unnecessarily confusing and has some bad side effects, like not being able to declare later variables in the same scope with the same type. This causes the compiler to complain and die on things like Address Address. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2013-06-09ruby: stats: use gem5's stats for cache and memory controllersNilay Vaish
This moves event and transition count statistics for cache controllers to gem5's statistics. It does the same for the statistics associated with the memory controller in ruby. All the cache/directory/dma controllers individually collect the event and transition counts. A callback function, collateStats(), has been added that is invoked on the controller version 0 of each controller class. This function adds all the individual controller statistics to a vector variables. All the code for registering the statistical variables and collating them is generated by SLICC. The patch removes the files *_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for collecting and dumping statistics respectively.
2013-05-21ruby: slicc: fix error msg in TypeFieldMemberAST.pyMalek Musleh
2013-05-21ruby: add stats to .sm files, remove cache profilerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E)
This patch changes the way cache statistics are collected in ruby. As of now, there is separate entity called CacheProfiler which holds statistical variables for caches. The CacheMemory class defines different functions for accessing the CacheProfiler. These functions are then invoked in the .sm files. I find this approach opaque and prone to error. Secondly, we probably should not be paying the cost of a function call for recording statistics. Instead, this patch allows for accessing statistical variables in the .sm files. The collection would become transparent. Secondly, it would happen in place, so no function calls. The patch also removes the CacheProfiler class. --HG-- rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py
2013-04-09Ruby: Add field to slicc machine for generic typeJoel Hestness
This allows you to have (i.e.) an L2 cache that is not named "L2Cache" but is still a GenericMachineType_L2Cache. This is particularly helpful if the protocol has multiple L2 controllers.
2013-04-09Ruby: Order profilers based on versionJoel Hestness
When Ruby stats are printed for events and transitions, they include stats for all of the controllers of the same type, but they are not necessarily printed in order of the controller ID "version", because of the way the profilers were added to the profiler vector. This patch fixes the push order problem so that the stats are printed in ascending order 0->(# controllers), so statistics parsers may correctly assume the controller to which the stats belong.
2013-04-09Ruby: Fix typo in Slicc if-statement AST errorJason Power
The error in the SLICC code was hidden by the python error in SLICC parser before this patch
2013-03-22ruby: slicc: set sender, receiver clock objs for optional queueNilay Vaish
2013-03-22slicc: remove check if the L1Cache has a sequencerNilay Vaish
2013-03-22ruby: move stall and wakeup functions to AbstractControllerNilay Vaish
These functions are currently implemented in one of the files related to Slicc. Since these are purely C++ functions, they are better suited to be in the base class.
2013-03-22ruby: connect two controllers using only message buffersNilay Vaish
This patch modifies ruby so that two controllers can be connected to each other with only message buffers in between. Before this patch, all the controllers had to be connected to the network for them to communicate with each other. With this patch, one can have protocols where a controller is not connected to the network, but communicates with another controller through a message buffer.
2013-02-19slicc: remove unused variable message_buffer_namesNilay Vaish
2013-02-10ruby: enable multiple clock domainsNilay Vaish
This patch allows ruby to have multiple clock domains. As I understand with this patch, controllers can have different frequencies. The entire network needs to run at a single frequency. The idea is that with in an object, time is treated in terms of cycles. But the messages that are passed from one entity to another should contain the time in Ticks. As of now, this is only true for the message buffers, but not for the links in the network. As I understand the code, all the entities in different networks (simple, garnet-fixed, garnet-flexible) should be clocked at the same frequency. Another problem is that the directory controller has to operate at the same frequency as the ruby system. This is because the memory controller does not make use of the Message Buffer, and instead implements a buffer of its own. So, it has no idea of the frequency at which the directory controller is operating and uses ruby system's frequency for scheduling events.
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
This patch is as of now the final patch in the series of patches that replace Time with Cycles.This patch further replaces Time with Cycles in Sequencer, Profiler, different protocols and related entities. Though Time has not been completely removed, the places where it is in use seem benign as of now.
2013-02-10ruby: replace Time with Cycles in Message classNilay Vaish
Concomitant changes are being committed as well, including the io operator<< for the Cycles class.
2013-02-10ruby: replaces Time with Cycles in many placesNilay Vaish
The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
2013-02-10ruby: record fully busy cycle with in the controllerNilay Vaish
This patch does several things. First, the counter for fully busy cycles for a controller is now kept with in the controller, instead of being part of the profiler. Second, the topology class no longer keeps an array of controllers which was only used for printing stats. Instead, ruby system will now ask each controller to print the stats. Thirdly, the statistical variable for recording how many different types were created is being moved in to the controller from the profiler. Note that for printing, the profiler will collate results from different controllers.
2013-01-28ruby: remove call to curCycle in panic()Nilay Vaish
The panic() function already prints the current tick value. This call to curCycle() is as such redundant. Since we are trying to move towards multiple clock domains, this call will print misleading time.
2013-01-14Ruby: remove reference to g_system_ptr from class MessageNilay Vaish
This patch was initiated so as to remove reference to g_system_ptr, the pointer to Ruby System that is used for getting the current time. That simple change actual requires changing a lot many things in slicc and garnet. All these changes are related to how time is handled. In most of the places, g_system_ptr has been replaced by another clock object. The changes have been done under the assumption that all the components in the memory system are on the same clock frequency, but the actual clocks might be distributed.
2013-01-14Ruby: use ClockedObject in Consumer classNilay Vaish
Many Ruby structures inherit from the Consumer, which is used for scheduling events. The Consumer used to relay on an Event Manager for scheduling events and on g_system_ptr for time. With this patch, the Consumer will now use a ClockedObject to schedule events and to query for current time. This resulted in several structures being converted from SimObjects to ClockedObjects. Also, the MessageBuffer class now requires a pointer to a ClockedObject so as to query for time.
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
The patch adds support to slicc for recognizing arguments that should be passed to the constructor of a class. I did not like the fact that an explicit check was being carried on the type 'TBETable' to figure out the arguments to be passed to the constructor. The patch also moves some of the member variables that are declared for all the controllers to the base class AbstractController.
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
2012-10-15ruby: improved support for functional accessesNilay Vaish
This patch adds support to different entities in the ruby memory system for more reliable functional read/write accesses. Only the simple network has been augmented as of now. Later on Garnet will also support functional accesses. The patch adds functional access code to all the different types of messages that protocols can send around. These messages are functionally accessed by going through the buffers maintained by the network entities. The patch also rectifies some of the bugs found in coherence protocols while testing the patch. With this patch applied, functional writes always succeed. But functional reads can still fail.
2012-10-15ruby: allow function definition in slicc structsNilay Vaish
This patch adds support for function definitions to appear in slicc structs. This is required for supporting functional accesses for different types of messages. Subsequent patches will use this to development.
2012-10-02ruby: rename template_hack to templateNilay Vaish
I don't like using the word hack. Hence, the patch.
2012-10-02ruby: remove some unused things in sliccNilay Vaish
This patch removes the parts of slicc that were required for multi-chip protocols. Going ahead, it seems multi-chip protocols would be implemented by playing with the network itself.
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish
This patch removes the use of g_system_ptr for event scheduling. Each consumer object now needs to specify upfront an EventManager object it would use for scheduling events. This makes the ruby memory system more amenable for a multi-threaded simulation.
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
Also allows for header files which are required in slicc generated code to be in a directory other than src/mem/ruby/slicc_interface.
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
This patch moves Ruby System from being a SimObject to recently introduced ClockedObject.
2012-09-10Ruby Slicc: remove the call to cin.get() functionNilay Vaish
If I understand correctly, this was put in place so that a debugger can be attached when the protocol aborts. While this sounds useful, it is a problem when the simulation is not being actively monitored. I think it is better to remove this.
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem or themselves for scheduling events.
2012-07-10imported patch jason/slicc-external-structure-fixBrad Beckmann
2012-07-10ruby: banked cache array resource modelBrad Beckmann
This patch models a cache as separate tag and data arrays. The patch exposes the banked array as another resource that is checked by SLICC before a transition is allowed to execute. This is similar to how TBE entries and slots in output ports are modeled.
2012-07-10ruby: tag and data cache access supportJoel Hestness
Updates to Ruby to support statistics counting of cache accesses. This feature serves multiple purposes beyond simple stats collection. It provides the foundation for ruby to model the cache tag and data arrays as physical resources, as well as provide the necessary input data for McPAT power modeling.
2012-07-10ruby: memory controllers now inherit from an abstract "MemoryControl" classNuwan Jayasena
2012-04-14clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6Andreas Hansson
This patch addresses a number of minor issues that cause problems when compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it avoids using the deprecated ext/hash_map and instead uses unordered_map (and similarly so for the hash_set). To make use of the new STL containers, g++ and clang has to be invoked with "-std=c++0x", and this is now added for all gcc versions >= 4.6, and for clang >= 3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1 unordered_map to avoid the deprecation warning. The addition of c++0x in turn causes a few problems, as the compiler is more stringent and adds a number of new warnings. Below, the most important issues are enumerated: 1) the use of namespaces is more strict, e.g. for isnan, and all headers opening the entire namespace std are now fixed. 2) another other issue caused by the more stringent compiler is the narrowing of the embedded python, which used to be a char array, and is now unsigned char since there were values larger than 128. 3) a particularly odd issue that arose with the new c++0x behaviour is found in range.hh, where the operator< causes gcc to complain about the template type parsing (the "<" is interpreted as the beginning of a template argument), and the problem seems to be related to the begin/end members introduced for the range-type iteration, which is a new feature in c++11. As a minor update, this patch also fixes the build flags for the clang debug target that used to be shared with gcc and incorrectly use "-ggdb".
2012-04-12Ruby: Ensure order-dependent iteration uses an ordered mapAndreas Hansson
This patch fixes a bug in Ruby that caused non-deterministic simulation when changing the underlying hash map implementation. The reason is order-dependent behaviour in combination with iteration over the hash map contents. The two locations where a sorted container is assumed are now changed to make use of a std::map instead of the unordered hash map. With this change, the stats changes slightly and the follow-on changeset will update the relevant statistics.
2012-04-06slicc: Controllers attached to Sequencers no longer have to be named L1Cache.Lisa Hsu