gem5 - gem5

Age	Commit message (Collapse)	Author
2006-11-12	Don't insert reponses into the list more than once	Ron Dreslinski
	If you get inserted in the front, reschedule the event --HG-- extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965
2006-11-10	Big fix for functional access, where we forgot to copy the last byte on ↵	Ron Dreslinski
	write intersections. src/mem/packet.cc: Make sure to copy the whole data (we were one byte short) src/mem/tport.cc: Fix for the proper semantics of fixPacket --HG-- extra : convert_revision : 215e05db9099d427afd4994f5b29079354c847d8
2006-10-31	add the ability to insert into the middle of the timing port send list	Ali Saidi
	--HG-- extra : convert_revision : 5422025f74ba7013f98d1d1dcbd1070f580aae61
2006-10-25	Fix simple timing port keep a list of all packets, have only one event, and ↵	Ali Saidi
	scan all packets on a functional access. --HG-- extra : convert_revision : c735a6408443b5cc90d1c1841c7aeb61e02ec6ae
2006-10-20	Get rid of a variable put back by merge.	Ron Dreslinski
	--HG-- extra : convert_revision : 5ddb6ae5d5412f062c07c16a27b79483430b5f22
2006-10-20	Merge zizzer:/bk/newmem	Ron Dreslinski
	into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/tport.cc: Merge PacketPtr changes --HG-- extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20	Use fixPacket function everywhere.	Ron Dreslinski
	Fix fixPacket assert function. Stop timing port from forwarding the request if a response was found in its queue on a read. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/python/m5/objects/MemTest.py: Add parameter to configure what percentage of mem accesses are functional src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Use fix Packet function src/mem/packet.cc: Fix an assert that was checking the wrong thing src/mem/tport.cc: Properly detect if we need to do the access to the functional device --HG-- extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20	Use PacketPtr everywhere	Nathan Binkert
	--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-17	Fixes to cache eliminating the assumption that the Packet is still valid ↵	Ron Dreslinski
	after sending out a request. Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-12	replace functional code in tport with fixPacket().	Ali Saidi
	fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address. --HG-- extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
2006-10-12	Check the response queue on functional accesses.	Ron Dreslinski
	The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses? src/mem/cache/base_cache.cc: src/mem/tport.cc: Add in functional check of retry queued packets. --HG-- extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-11	Fix bus in FS mode.	Ron Dreslinski
	src/mem/bus.cc: Add debugging statement src/mem/bus.hh: Fix implementation of bus for subsequent recvTimings while handling a retry request. src/mem/tport.cc: Rework timing port to retry properly --HG-- extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
2006-10-10	Changed the bus to use a bool to keep track of retries rather than a pointer	Gabe Black
	src/mem/tport.cc: minor formatting tweak --HG-- extra : convert_revision : 7391d142815c5876fcc0f991bd053e6a1781c101
2006-10-10	Fixed a bug where a packet was attempted to be sent even though another ↵	Gabe Black
	packet was waiting for the bus. --HG-- extra : convert_revision : 29f7a4f676884330d7b7e93517dea85fc7bbf678
2006-10-08	Only respond if the pkt needs a response.	Ron Dreslinski
	Fix an issue with memory handling writebacks. src/mem/cache/base_cache.hh: src/mem/tport.cc: Only respond if the pkt needs a response. src/mem/physical.cc: Make physical memory respond to writebacks, set satisfied for invalidates/upgrades. --HG-- extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
2006-08-30	Move more common functionality into SimpleTimingPort,	Steve Reinhardt
	allowing derived classes to be simplified. --HG-- extra : convert_revision : c980d3aec5e6c044d8f41e96252726fe9a256605
2006-07-20	Move PioPort timing code into Simple Timing Port object	Ali Saidi
	Make PioPort use it Make Physical memory use it as well src/SConscript: Add timing port to sconscript src/dev/io_device.cc: src/dev/io_device.hh: Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory src/mem/physical.cc: src/mem/physical.hh: use a simple timing port stuff instead of rolling our own here --HG-- extra : convert_revision : e5befbd295a572568cfdca533efb5ed1984c59d1