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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
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src
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mem
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xbar.cc
Age
Commit message (
Expand
)
Author
2019-09-30
mem: Use new-style stats in the XBar models
Andreas Sandberg
2019-08-27
cpu, dev, mem: Use the new Port methods.
Gabe Black
2019-04-28
mem: Minimize the use of MemObject.
Gabe Black
2019-03-26
mem: Clean up the xbars a little.
Gabe Black
2019-03-19
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Gabe Black
2018-06-19
mem: Use address range to find the destination port in the xbar
Nikos Nikoleris
2018-06-19
mem: Use the caching built into AddrRangeMap in the xbar
Gabe Black
2018-06-19
base, mem: Disambiguate if an addr range is contained or overlaps
Nikos Nikoleris
2017-12-04
misc: Rename misc.(hh|cc) to logging.(hh|cc)
Gabe Black
2017-06-20
mem: Replace EventWrapper use with EventFunctionWrapper
Sean Wilson
2016-11-09
style: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter
2016-06-06
sim: Call regStats of base-class as well
Stephan Diestelhorst
2015-07-07
sim: Refactor and simplify the drain API
Andreas Sandberg
2015-03-02
mem: Add crossbar latencies
Marco Balboni
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-02-11
mem: Clarification of packet crossbar timings
Marco Balboni
2014-09-27
mem: Output precise range when XBar has conflicts
Curtis Dunham
2014-09-20
mem: Rename Bus to XBar to better reflect its behaviour
Andreas Hansson