index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
mem
/
xbar.hh
Age
Commit message (
Expand
)
Author
2019-09-30
mem: Use new-style stats in the XBar models
Andreas Sandberg
2019-04-28
mem: Minimize the use of MemObject.
Gabe Black
2019-03-26
mem: Deleting this init() method was accidentally dropped during rebase.
Gabe Black
2019-03-26
mem: Clean up the xbars a little.
Gabe Black
2019-03-23
misc: missing override specifier
Andrea Mondelli
2019-03-19
arch, cpu, dev, gpu, mem, sim, python: start using getPort.
Gabe Black
2018-06-19
mem: Use address range to find the destination port in the xbar
Nikos Nikoleris
2018-06-19
mem: Use the caching built into AddrRangeMap in the xbar
Gabe Black
2017-06-20
mem: Replace EventWrapper use with EventFunctionWrapper
Sean Wilson
2016-12-19
mem: Make the BaseXBar public to not confuse Python wrappers
Andreas Sandberg
2015-11-03
mem: hmc: minor fixes
Erfan Azarkhish
2015-10-12
misc: Remove redundant compiler-specific defines
Andreas Hansson
2015-07-07
sim: Refactor and simplify the drain API
Andreas Sandberg
2015-07-07
sim: Decouple draining from the SimObject hierarchy
Andreas Sandberg
2015-07-03
mem: Delay responses in the crossbar before forwarding
Andreas Hansson
2015-03-02
mem: Add crossbar latencies
Marco Balboni
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-02-11
mem: Clarification of packet crossbar timings
Marco Balboni
2015-01-22
mem: Make the XBar responsible for tracking response routing
Andreas Hansson
2014-09-20
mem: Rename Bus to XBar to better reflect its behaviour
Andreas Hansson