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Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
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The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
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Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.
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1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
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This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
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cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
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that the cache can make context-specific decisions within their various tag policy implementations.
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The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.
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Added error message when a symbol is not an instance of a particular expected
type.
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* * *
ruby: Removed primitive .hh includes
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These files are need by the MOESI_CMP_token protocol.
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Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
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Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
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Added default names to message buffers created by the simple network.
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Added error message when a method call is not supported by an object.
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Small fix to the State Machine error message when duplicate actions are defined.
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Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared
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Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
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Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
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Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
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random arbitrate
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