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AgeCommit message (Expand)Author
2015-07-20ruby: change router pipeline stages to 2David Hashe
2015-07-20ruby: change advance_stage for flit_dDavid Hashe
2015-07-20slicc: improved stalling support in protocolsBrad Beckmann
2015-07-20ruby: expose access permission to replacement policiesDavid Hashe
2015-07-20ruby: adds size and empty apis to the msg buffer stallmapDavid Hashe
2015-07-20ruby: fix deadlock bug in banked array resource checksDavid Hashe
2015-07-20ruby: Fix for stallAndWait bugDavid Hashe
2015-07-20mem: add request types for acquire and releaseDavid Hashe
2015-07-20ruby: allocate a block in CacheMemory without updating LRU stateDavid Hashe
2015-07-20ruby: speed up function used for cache walksDavid Hashe
2015-07-20slicc: support for arbitrary DPRINTF flags (not just RubySlicc)David Hashe
2015-07-20slicc: support for local variable declarations in action blocksDavid Hashe
2015-07-20ruby: initialize replacement policies with their own simobjsDavid Hashe
2015-07-20ruby: give access to cache tag/data latencies from SLICCDavid Hashe
2015-07-20slicc: support for multiple cache entry types in the same state machineDavid Hashe
2015-07-20slicc: Fix bug in enqueue and peek statements.David Hashe
2015-07-20slicc: fix missing inline function in LocalVariableASTDavid Hashe
2015-07-20slicc: improve support for prefix operationsDavid Hashe
2015-07-20slicc: support for transitions with a wildcard next stateDavid Hashe
2015-07-20slicc: support for multiple message types on the same bufferDavid Hashe
2015-08-01slicc: fatal->panic on invalid transitionsBrad Beckmann
2015-07-20mem: Hit callback delay fixDavid Hashe
2015-07-20ruby: re-added the addressToInt slicc interface functionBrad Beckmann
2015-07-20ruby: add useful dprints to sequencerBrad Beckmann
2015-07-20slicc: isinstance bugfixDavid Hashe
2015-07-30mem: Add missing clean eviction on uncacheable accessAndreas Hansson
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
2015-07-30mem: Make caches way awareDavid Guillen-Fandos
2015-07-30mem: Transition away from isSupplyExclusive for writebacksAndreas Hansson
2015-07-30mem: Tidy up CacheBlk classAndreas Hansson
2015-07-30mem: Tidy up packetAndreas Hansson
2015-07-24ruby: dma sequencer: removes redundant codeBrandon Potter
2015-07-22ruby: network: NetworkLink inherits from Consumer now.Nilay Vaish
2015-07-13mem: Fix (ab)use of emplace to avoid temporary object creationAndreas Hansson
2015-07-13mem: Updated DRAMSim2 wrapper to new drain APIAndreas Hansson
2015-07-10ruby: replace global g_abs_controls with per-RubySystem varBrandon Potter
2015-07-10ruby: replace global g_system_ptr with per-object pointersBrandon Potter
2015-07-10ruby: replace g_ruby_start with per-RubySystem m_start_cycleBrandon Potter
2015-07-10ruby: remove extra whitespace and correct misspelled wordsBrandon Potter
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-06mem: Cleanup CommMonitor in preparation for probe supportAndreas Sandberg
2015-07-04mem: packet: Add const to constructor argumentNilay Vaish
2015-07-04ruby: drop NetworkMessage classNilay Vaish
2015-07-04ruby: mesi three level: name change to avoid clashNilay Vaish
2015-07-04ruby: remove message buffer nodeNilay Vaish
2015-07-03mem: Increase the default buffer sizes for the DDR4 controllerAndreas Hansson
2015-07-03mem: Update DRAM command scheduler for bank groupsWendy Elsasser
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