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2007-06-27Get rid of coherence protocol object.Steve Reinhardt
--HG-- extra : convert_revision : 4ff144342dca23af9a12a2169ca318a002654b42
2007-06-26Revamp replacement-of-upgrade handling.Steve Reinhardt
--HG-- extra : convert_revision : 9bc09d8ae6d50e6dfbb4ab21514612f9aa102a2e
2007-06-26Handle deferred snoops better.Steve Reinhardt
--HG-- extra : convert_revision : 703da6128832eb0d5cfed7724e5105f4b3fe4f90
2007-06-26cache_impl.hh:Steve Reinhardt
Change target overflow from assertion to warning. src/mem/cache/cache_impl.hh: Change target overflow from assertion to warning. --HG-- extra : convert_revision : ceca990ed916bbf96dedd4836c40df522803f173
2007-06-26Handle replacement of block with pending upgrade.Steve Reinhardt
src/mem/cache/tags/lru.cc: Add some replacement DPRINTFs --HG-- extra : convert_revision : 7993ec24d6af7e7774d04ce36f20e3f43f887fd9
2007-06-25Couple minor bug fixes...Steve Reinhardt
src/mem/cache/cache_impl.hh: Handle grants with no packet. src/mem/cache/miss/mshr.cc: Fix MSHR snoop hit handling. --HG-- extra : convert_revision : f365283afddaa07cb9e050b2981ad6a898c14451
2007-06-25Get rid of requestCauses. Use timestamped queue to makeSteve Reinhardt
sure we don't re-request bus prematurely. Use callback to avoid calling sendRetry() recursively within recvTiming. --HG-- extra : convert_revision : a907a2781b4b00aa8eb1ea7147afc81d6b424140
2007-06-24Better handling of deferred targets.Steve Reinhardt
--HG-- extra : convert_revision : 0fbc28c32c1eeb3dd672df14c1d53bd516f81d0f
2007-06-23Minor fix plus new assertion to catch similar bugs.Steve Reinhardt
src/cpu/memtest/memtest.cc: Need to set packet source field so that response from cache doesn't run into assertion failure when copying source to dest. src/mem/packet.hh: Copy source field when copying packets. Assert that source is valid before copying it to dest when turning packets around. --HG-- extra : convert_revision : 09e3cfda424aa89fe170e21e955b295746832bf8
2007-06-22Fixes to hitLatency, blocking, buffer allocation.Steve Reinhardt
Single-cpu timing mode seems to work now. --HG-- extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad
2007-06-21Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
2007-06-21Getting closer...Steve Reinhardt
configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we ↵Ali Saidi
don't spend so much time calling malloc() --HG-- extra : convert_revision : a946564eee46ed7d2aed41c32d488ca7f036c32f
2007-06-20Minor error.Vincentius Robby
--HG-- extra : convert_revision : 514032e21c8861f20fcbcae7204e132088cc7dbc
2007-06-20Removed "adding instead of dividing" trick.Vincentius Robby
Caused slowdown in performance instead of speeding up. src/cpu/base.cc: Removed "adding instead of dividing" trick. src/mem/bus.cc: Fixed spelling in comments. Removed "adding instead of dividing" trick. --HG-- extra : convert_revision : 65a736f4f09a64e737dc7aeee53b117976330488
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
supposed to and make sure parameters have the right type. Also make sure that any object that should be an intermediate type has the right options set. --HG-- extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
2007-06-17Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 configs/example/memtest.py: Hand merge redundant changes. --HG-- extra : convert_revision : a2e36be254bf052024f37bcb23b5209f367d37e1
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-06-09Add a startup function that will fast forward to the right clock edgeNathan Binkert
using a divide in order to not loop forever after resuming from a checkpoint --HG-- extra : convert_revision : 4bbc70b1be4e5c4ed99d4f88418ab620d5ce475a
2007-06-09More realistic parametersNathan Binkert
--HG-- extra : convert_revision : aaa4ea2b7c97df3d6b731e9252984b45715e9d6f
2007-06-05Clean up some of vincent's code and commit itAli Saidi
Makes page table cache scheme actually work src/mem/page_table.cc: src/mem/page_table.hh: fix caching scheme to actually work and improve performance --HG-- extra : convert_revision : 443a8d8acbee540b26affcfdfbf107b8e735d1bd
2007-05-29Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 26921dad179699b7868768361143aaa8d790b8fc
2007-05-30tport.cc:Steve Reinhardt
Oops... forgot to update call site after changing function argument semantics. src/mem/tport.cc: Oops... forgot to update call site after changing function argument semantics. --HG-- extra : convert_revision : 9234b991dc678f062d268ace73c71b3d13dd17dc
2007-05-29Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 72c6f2ce7e9e2b46e59711a2c3cfe770c243018e
2007-05-29A little more cleanup & refactoring of SimpleTimingPort.Steve Reinhardt
Make it a better base class for cache ports. --HG-- extra : convert_revision : 37d6de11545a68c1a7d11ce33fe5971c51434ee4
2007-05-28Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 6f462916cb0eb309b6799e94fbf07629abb50eba
2007-05-28Restructure SimpleTimingPort a bit:Steve Reinhardt
- factor out checkFunctional() code so it can be called from derived classes - use EventWrapper for sendEvent, move event handling code from event to port where it belongs - make sendEvent a pointer so derived classes can override it - replace std::pair with new class for readability --HG-- extra : convert_revision : 5709de2daacfb751a440144ecaab5f9fc02e6b7a
2007-05-28Reformat comments to meet line length restriction.Steve Reinhardt
--HG-- extra : convert_revision : 24c00ec4904d9fb4d6e39521e0ff8b8f60d60f6a
2007-05-27Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : fba7efd444e1ca9738385dd4662a33feab357e79
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-22Fix getDeviceAddressRanges() to get snooping right.Steve Reinhardt
--HG-- extra : convert_revision : 2aeab25ef955ab9db7b968786faff227239fbbe4
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/mem/cache/base_cache.hh: Manual conflict resolution. --HG-- extra : convert_revision : 5ebfd7abb4f978caa88bf43d25935869edfc6b9f
2007-05-22Another pass of minor changes in preparation for new protocol.Steve Reinhardt
src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: Get rid of old invalidate propagation logic in preparation for new multilevel snoop protocol. src/mem/cache/coherence/coherence_protocol.cc: L2 cache now has protocol, so protocol must handle ReadExReq coming in from the CPU side. src/mem/cache/miss/mshr_queue.cc: Assertion is failing, so let's take it out for now. src/mem/packet.cc: src/mem/packet.hh: Add WritebackAck command. Reorganize enum to put responses next to corresponding requests. Get rid of unused WriteReqNoAck. --HG-- extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-20Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : a8efe71a50b9ae480c5ad0aabd7aa9ba22bc2968
2007-05-20Insist that PhysicalMemory object have at least one connection.Steve Reinhardt
--HG-- extra : convert_revision : 36c33d25a3b23ac2094577aa504c24fac0f3ffcc
2007-05-18Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 src/mem/bridge.cc: SCCS merged --HG-- extra : convert_revision : 9492be56a305afe88f28a77c3b23e80ce6aa81b3
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
Compiles but doesn't work... committing just so I can merge (stupid bk!). src/mem/bridge.cc: Get rid of SNOOP_COMMIT. src/mem/bus.cc: src/mem/packet.hh: Get rid of SNOOP_COMMIT & two-pass snoop. First bits of EXPRESS_SNOOP support. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/prefetch/base_prefetcher.cc: Big reorg of ports and port-related functions & events. src/mem/cache/cache.cc: src/mem/cache/cache_builder.cc: src/mem/cache/coherence/SConscript: Get rid of UniCoherence object. --HG-- extra : convert_revision : 7672434fa3115c9b1c94686f497e57e90413b7c3
2007-05-19Oops... some places in C++ explicitly ask for a "functional"Steve Reinhardt
port. It would be better to move this to python IMO but for now I'll stick in a compatibility hack. --HG-- extra : convert_revision : a81a29cbd43becd0e485559eb7b2a31f7a0b082d
2007-05-19PhysicalMemory has vector of uniform ports instead of one special one.Steve Reinhardt
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
2007-05-15Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 32dc1bec7fdb1ecb8879ed2dd745c4b23929aeab
2007-05-15hopefully the final hacky change to make the bus bridge work okAli Saidi
cache blocks that get dmaed ARE NOT marked invalid in the caches so it's a performance issue here src/mem/bridge.cc: src/mem/bridge.hh: hopefully the final hacky change to make the bus bridge work ok --HG-- extra : convert_revision : 62cbc65c74d1a84199f0a376546ec19994c5899c
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 8a501917daf81021212d136b4ebbfa059b452a13
2007-05-14add uglyiness to fix dmasAli Saidi
src/dev/io_device.cc: extra printing and assertions src/mem/bridge.hh: deal with packets only satisfying part of a request by making many requests src/mem/cache/cache_impl.hh: make the cache try to satisfy a functional request from the cache above it before checking itself --HG-- extra : convert_revision : 1df52ab61d7967e14cc377c560495430a6af266a
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
RequestEvent and ResponseEvent. Compiles but not tested. --HG-- extra : convert_revision : cc791e7adea5b0406e986a0076edba51856b9105
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
Compiles but not tested. --HG-- extra : convert_revision : 4e1e28c4b87721ccfcf35a5ea62c1fa324acbaf9
2007-05-13fix handling of atomic packetsAli Saidi
fix up code for counting requests and responses --HG-- extra : convert_revision : 0d70981ee41c5d9c36cad01bd505281a096f6119
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1
2007-05-09undo my previous bus change, it can make the bus deadlock.. so it still ↵Ali Saidi
constantly reschedules itself --HG-- extra : convert_revision : b5ef1aa0a6a2e32bd775d2dbcad9cd9505ad9b78
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list --HG-- extra : convert_revision : 3595ad932015a4ce2bb72772da7850ad91bd09b1
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 15:00:06 +0000