Age | Commit message (Collapse) | Author |
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?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
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extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
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Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
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extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
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src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
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extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
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configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
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Factor out some asserts that were on both
sides of an if/else.
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Reindent due to resulting changes in nesting.
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but not on zizzer... g++ 4 thing maybe?)
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things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
add code to serialize/unserialize process
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extra : convert_revision : ee9eb5e2c38c5d317a2f381972c552d455e0db9e
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Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
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extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
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after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
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extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
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writebacks delete the packet.
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extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
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sendTiming.
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
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extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : f62790e46a7e3eb88a6f8c7bfaa08526285248a3
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Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
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extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
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fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.
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into zeep.pool:/z/saidi/work/m5.newmem.head
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : fa5b2cfa79d87a0612b8116d407a8b2959d9095a
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src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
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extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
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into zeep.pool:/z/saidi/work/m5.newmem.head
src/mem/packet.hh:
hand merge
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extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
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implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such
src/base/traceflags.py:
add a traceflag for functional accesses
src/mem/packet.cc:
implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
add the ability to print a packet to an ostream
remove tabs in file
mark const functions as such
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extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
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The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
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extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
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src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
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extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
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Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
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extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
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src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
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extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
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src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
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Fix bug with deadlocking
src/mem/cache/base_cache.cc:
Make sure to not wait anymore
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case as well when dealing with grants that aren't used.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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some reason.
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src/mem/cache/base_cache.cc:
When turning asserts into if's don't forget to invert.
Must be too sleepy.
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uprgades to owned blocks hit in the WB buffer
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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extra : convert_revision : eaae105025635c37af06cf72bb061ce82def9dc9
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src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
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extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
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try to send another packet while it's still waiting for the bus.
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