summaryrefslogtreecommitdiff
path: root/src/mem
AgeCommit message (Expand)Author
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-01-22ruby: removed Write_Only AccessPermissionBrad Beckmann
2015-07-20ruby: split CPU and GPU latency statsDavid Hashe
2016-01-19gpu-compute: AMD's baseline GPU modelTony Gutierrez
2016-01-19mem: write combining for ruby protocolsTony Gutierrez
2016-01-19* * *Tony Gutierrez
2015-07-20mem: misc flags for AMD gpu modelBlake Hechtman
2016-01-11mem: fix bug in packet access endianness changesSteve Reinhardt
2016-01-11scons: Enable -Wextra by defaultAndreas Hansson
2015-12-31mem: add CacheVerbose debug flag, filter noisy DPRINTFsSteve Reinhardt
2015-12-31mem: Do not rely on the NeedsWritable flag for responsesAndreas Hansson
2015-12-31mem: Do not allocate space for packet data if not neededAndreas Hansson
2015-12-31mem: Do not alter cache block state on uncacheable snoopsAndreas Hansson
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-07-20ruby: slicc: have a static MachineTypeTony Gutierrez
2015-07-20ruby: slicc: remove support for single machine, multiple typesTony Gutierrez
2015-12-28mem: Explicitly check MSHR snoops for cases not dealt withAndreas Hansson
2015-12-28mem: Remove unused cache squash functionalityAndreas Hansson
2015-12-28mem: Avoid unecessary checks when creating HardPFReq in cacheAndreas Hansson
2015-12-28mem: Do not use sender state to track forwarded snoops in cacheAndreas Hansson
2015-12-28mem: Fix cache sender state handling and add clarificationAndreas Hansson
2015-12-17mem: Fix memory allocation bug in deferred snoop handlingAndreas Hansson
2015-07-20mem: add request types for acquire and releaseDavid Hashe
2015-07-20ruby: more flexible ruby tester supportBrad Beckmann
2015-12-09mem: remove acq/rel cmds from packet and add mem fence reqTony Gutierrez
2015-12-07cpu: Support virtual addr in elastic tracesRadhika Jagtap
2015-12-07mem: Add instruction sequence number to requestRadhika Jagtap
2015-11-25mem: Fix search-replace issues in DRAMPower wrapper licenseAndreas Hansson
2015-11-15arm: Add missing explicit overrides for classic cachesAndreas Sandberg
2015-07-20ruby: added stl vector of ints to be used by SLICCBrad Beckmann
2015-11-13slicc: fixes for the Address to Addr changeset (11025)Tony Gutierrez
2015-11-13ruby: add BoolVecJoe Gross
2015-07-20mem: add boolean to disable PacketQueue's size sanity checkBrad Beckmann
2015-11-06mem: Add an option to perform clean writebacks from cachesAndreas Hansson
2015-11-06mem: Add cache clusivityAndreas Hansson
2015-11-06mem: Avoid unnecessary snoops on writebacks and clean evictionsAli Jafri
2015-11-06mem: Order packet queue only on matching addressesAndreas Hansson
2015-11-06mem: Enforce insertion order on the cache response pathAli Jafri
2015-11-06mem: Use the packet delays and do not just zero them outAndreas Hansson
2015-11-06mem: Align rules for sinking inhibited packets at the slaveAndreas Hansson
2015-11-06mem: Do not treat CleanEvict as a write operationAndreas Hansson
2015-11-06mem: Unify delayed packet deletionAndreas Hansson
2015-11-06misc: Appease clang static analyzerAndreas Hansson
2015-11-06mem: Check the XBar's port queues on functional snoopsAndreas Sandberg
2015-11-03mem: hmc: minor fixesErfan Azarkhish
2015-11-03mem: hmc: serial link modelErfan Azarkhish
2015-11-03mem: hmc: adds controllerErfan Azarkhish
2015-10-29mem: Clarify cache MSHR handling on fillAndreas Hansson
2015-10-23x86: Add missing explicit overrides for X86 devicesAndreas Hansson
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 15:57:50 +0000