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path: root/src/mem
AgeCommit message (Expand)Author
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
2015-03-02mem: Add crossbar latenciesMarco Balboni
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-03-02mem: Fix prefetchSquash + memInhibitAsserted bugAli Jafri
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
2015-02-16mem: Fix initial value problem with MemCheckerStephan Diestelhorst
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
2015-02-16mem: Use the range cache for lookup as well as accessAndreas Hansson
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
2015-01-22mem: Remove unused Packet src and dest fieldsAndreas Hansson
2015-01-22mem: Remove Packet source from ForwardResponseRecordAndreas Hansson
2015-01-22mem: Remove unused RequestState in the bridgeAndreas Hansson
2015-01-22mem: Always use SenderState for response routing in RubyPortAndreas Hansson
2015-01-22mem: Make the XBar responsible for tracking response routingAndreas Hansson
2015-01-22mem: Clean up Request initialisationAndreas Hansson
2015-01-20mem: Fix bug in cache request retry mechanismAndreas Hansson
2015-01-20mem: Move DRAM interleaving check to initAndreas Hansson
2014-12-23mem: Change prefetcher to use random_mtMitch Hayenga
2014-12-23mem: Hide WriteInvalidate requests from prefetchersCurtis Dunham
2014-12-23mem: Fix event scheduling issue for prefetchesMitch Hayenga
2014-12-23mem: Fix bug relating to writebacks and prefetchesMitch Hayenga
2014-12-23mem: Rework the structuring of the prefetchersMitch Hayenga
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-12-23config: Expose the DRAM ranks as a command-line optionAndreas Hansson
2014-12-23mem: Ensure DRAM controller is idle when in atomic modeAndreas Hansson
2014-12-23mem: Add rank-wise refresh to the DRAM controllerOmar Naji
2014-12-23mem: Fix a bug in the DRAM controller arbitrationOmar Naji
2014-12-23mem: Add stack distance statistics to the CommMonitorKanishk Sugand
2014-12-23mem: Add a stack distance calculatorKanishk Sugand
2014-12-23mem: Add MemChecker and MemCheckerMonitorMarco Elver
2014-12-02mem: Support WriteInvalidate (again)Curtis Dunham
2014-12-02mem: Remove WriteInvalidate supportCurtis Dunham
2014-12-02mem: Relax packet src/dest check and shift onus to crossbarAndreas Hansson
2014-12-02mem: Clean up packet data allocationAndreas Hansson
2014-12-02mem: Cleanup Packet::checkFunctional and hasData usageAndreas Hansson
2014-12-02mem: Make the requests carried by packets constAndreas Hansson
2014-12-02mem: Make Request getters constAndreas Hansson
2014-12-02mem: Add checks and explanation for assertMemInhibit usageAndreas Hansson
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
2014-12-02mem: Remove redundant Packet::allocate callsAndreas Hansson
2014-12-02mem: Use const pointers for port proxy write functionsAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-12-02mem: Remove null-check bypassing in Packet::getPtrAndreas Hansson
2014-12-02mem: Add a GDDR5 DRAM configOmar Naji
2014-11-24misc: Another round of static analysis fixupsAndreas Hansson
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