summaryrefslogtreecommitdiff
path: root/src/mem
AgeCommit message (Expand)Author
2015-01-20mem: Fix bug in cache request retry mechanismAndreas Hansson
2015-01-20mem: Move DRAM interleaving check to initAndreas Hansson
2014-12-23mem: Change prefetcher to use random_mtMitch Hayenga
2014-12-23mem: Hide WriteInvalidate requests from prefetchersCurtis Dunham
2014-12-23mem: Fix event scheduling issue for prefetchesMitch Hayenga
2014-12-23mem: Fix bug relating to writebacks and prefetchesMitch Hayenga
2014-12-23mem: Rework the structuring of the prefetchersMitch Hayenga
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-12-23config: Expose the DRAM ranks as a command-line optionAndreas Hansson
2014-12-23mem: Ensure DRAM controller is idle when in atomic modeAndreas Hansson
2014-12-23mem: Add rank-wise refresh to the DRAM controllerOmar Naji
2014-12-23mem: Fix a bug in the DRAM controller arbitrationOmar Naji
2014-12-23mem: Add stack distance statistics to the CommMonitorKanishk Sugand
2014-12-23mem: Add a stack distance calculatorKanishk Sugand
2014-12-23mem: Add MemChecker and MemCheckerMonitorMarco Elver
2014-12-02mem: Support WriteInvalidate (again)Curtis Dunham
2014-12-02mem: Remove WriteInvalidate supportCurtis Dunham
2014-12-02mem: Relax packet src/dest check and shift onus to crossbarAndreas Hansson
2014-12-02mem: Clean up packet data allocationAndreas Hansson
2014-12-02mem: Cleanup Packet::checkFunctional and hasData usageAndreas Hansson
2014-12-02mem: Make the requests carried by packets constAndreas Hansson
2014-12-02mem: Make Request getters constAndreas Hansson
2014-12-02mem: Add checks and explanation for assertMemInhibit usageAndreas Hansson
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
2014-12-02mem: Remove redundant Packet::allocate callsAndreas Hansson
2014-12-02mem: Use const pointers for port proxy write functionsAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-12-02mem: Remove null-check bypassing in Packet::getPtrAndreas Hansson
2014-12-02mem: Add a GDDR5 DRAM configOmar Naji
2014-11-24misc: Another round of static analysis fixupsAndreas Hansson
2014-11-23mem: Page Table map api modificationAlexandru Dutu
2014-11-23mem: Multi Level Page Table bug fixAlexandru Dutu
2014-11-23mem: Page Table long linesAlexandru Dutu
2014-11-14mem: Clarify unit of DRAM controller buffer sizeAndreas Hansson
2014-11-12mem: Delete unused variable in Garnet NetworkLinkMitch Hayenga
2014-11-06ruby: provide a backing storeNilay Vaish
2014-11-06ruby: interface with classic memory controllerNilay Vaish
2014-11-06ruby: remove the function functionalReadBuffers()Nilay Vaish
2014-11-06ruby: coherence protocols: remove data block from dirctory entryNilay Vaish
2014-11-06ruby: slicc: allow adding a bool to an int, like C++.Nilay Vaish
2014-11-06ruby: remove sparse memory.Nilay Vaish
2014-11-06ruby: single physical memory in fs modeNilay Vaish
2014-11-06ruby: dma sequencer: remove RubyPort as parent classNilay Vaish
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-21mem: don't inhibit WriteInv's or defer snoops on their MSHRsCurtis Dunham
2014-10-29mem: have WriteInvalidate obsolete MSHRsCurtis Dunham
2014-10-20mem: Fix DRAM activationlLimit bugOmar Naji
2014-10-20mem: Add DRAM device size and check against configOmar Naji
2014-10-16mem: Modernise PhysicalMemory with C++11 featuresAndreas Hansson
2014-10-16misc: Move AddrRangeList from port.hh to addr_range.hhAndreas Hansson