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mem
Age
Commit message (
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Author
2014-01-29
mem: Allowed tagged instruction prefetching in stride prefetcher
Mitch Hayenga
2014-01-29
mem: prefetcher: add options, support for unaligned addresses
Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-28
mem: Remove redundant findVictim() input argument
Amin Farmahini
2014-01-28
mem: Fixes a bug in simple_dram write merging
Amin Farmahini
2014-01-24
cpu: Add support for instructions that zero cache lines.
Ali Saidi
2014-01-24
mem: Add flag to request if it was generated by a page table walk
Giacomo Gabrielli
2014-01-24
mem: Add support for a security bit in the memory system
Giacomo Gabrielli
2014-01-24
Cache: Collect very basic stats on tag and data accesses
Timothy M. Jones
2014-01-24
mem: per-thread cache occupancy and per-block ages
Dam Sunwoo
2014-01-24
mem: track per-request latencies and access depths in the cache hierarchy
Matt Horsnell
2014-01-17
ruby: remove unused label no_vector
Nilay Vaish
2014-01-10
ruby: move all statistics to stats.txt, eliminate ruby.stats
Nilay Vaish
2014-01-09
ruby: fix bug introduced to revision 8523754f8885
Nilay Vaish
2014-01-08
ruby: slicc: remove variable 'addr' used in calls to doTransition
Nilay Vaish
2014-01-04
ruby: add a three level MESI protocol.
Nilay Vaish
2014-01-04
ruby: rename MESI_CMP_directory to MESI_Two_Level
Nilay Vaish
2014-01-04
ruby: add support for clusters
Nilay Vaish
2014-01-04
ruby: some small changes
Nilay Vaish
2013-12-26
ruby: fix bugs in mesi cmp directory protocol
Nilay Vaish
2013-12-20
ruby: slicc: replace max_in_port_rank with number of inports
Nilay Vaish
2013-12-20
ruby: declare variables to be unsigned in Address.hh
Nilay Vaish
2013-12-20
ruby: mesi: remove owner and sharer fields from directory tags
Nilay Vaish
2013-11-01
mem: Fixes for DRAM stats accounting
Andreas Hansson
2013-11-01
mem: Fix the LPDDR3 page size
Andreas Hansson
2013-11-01
mem: Adding stats for DRAM power calculation
Neha Agarwal
2013-11-01
mem: Unify request selection for read and write queues
Neha Agarwal
2013-11-01
mem: Add a simple adaptive version of the open-page policy
Andreas Hansson
2013-11-01
mem: Just-in-time write scheduling in DRAM controller
Neha Agarwal
2013-11-01
mem: Add tRRD as a timing parameter for the DRAM controller
Andreas Hansson
2013-11-01
mem: Less conservative tRAS in DRAM configurations
Andreas Hansson
2013-11-01
mem: Make tXAW enforcement less conservative and per rank
Ani Udipi
2013-11-01
mem: Fix for 100% write threshold in DRAM controller
Neha Agarwal
2013-11-01
mem: Pick the next DRAM request based on bank availability
Andreas Hansson
2013-11-01
mem: Use the same timing calculation for DRAM read and write
Ani Udipi
2013-11-01
mem: Fix DRAM bank occupancy for streaming access
Ani Udipi
2013-11-01
mem: Schedule time for DRAM event taking tRAS into account
Ani Udipi
2013-11-01
mem: Add tRAS parameter to the DRAM controller model
Ani Udipi
2013-10-31
mem: Add "const" attribute to Packet getters
Stephan Diestelhorst
2013-10-31
mem: Add privilege info to request class
Prakash Ramrakhyani
2013-10-30
ruby: set SenderMachine in messages of MOESI_CMP_directory
Lluc Alvarez
2013-10-30
ruby: Fixed a deadlock when restoring a checkpoint with garnet
Emilio Castillo
2013-10-17
mem: De-virtualise interfaces in the CoherentBus
Stephan Diestelhorst
2013-10-17
cpu: add consistent guarding to *_impl.hh files.
Matt Horsnell
2013-10-17
mem: Add PortID to QueuedMasterPort constructor
Sascha Bischoff
2013-10-17
mem: Make MemoryAccess flag more verbose
Ali Saidi
2013-10-15
ruby: eliminate non-determinism from ruby.stats output
Steve Reinhardt
2013-10-15
mem: Rename the ASI_BITS flag field in Request
Andreas Sandberg
2013-10-15
mem: Use a flag instead of address bit 63 for generic IPRs
Andreas Sandberg
2013-09-18
mem: Fix scheduling bug in SimpleMemory
Andreas Hansson
2013-09-11
ruby: Fix Topology throttle connections
Joel Hestness
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