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2018-10-11mem-cache: Move sector_blks to tags folderDaniel R. Carvalho
Move sector_blks.hh and sector_blks.cc to the tags folder, as its usage scope is restricted to the tags, and caches should not be aware of them. Change-Id: Ia7a71f51ec251d827872daf108c87da543a0ba57 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13417 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Rename blk.cc/hh to cache_blk.cc/hhDaniel R. Carvalho
Rename the files blk.cc and blk.hh to cache_blk.cc and cache_blk.hh to comply with the usual file-class naming rules. Change-Id: I8af45df3e4b8dd934fd9929ec914fb230cb2cb09 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13416 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Virtualize block printDaniel R. Carvalho
Encapsulate and virtualize block print, so that relevant information can be easily printed anywhere. Change-Id: I91109c29c126755183a0fd2b4446f5335e64076b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13415 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-10mem-cache: Create Tree-PLRU replacement policyDaniel R. Carvalho
Implementation of a Tree-PLRU replacement policy. It is based on the assumption that a set associative cache is used. Change-Id: I74b227e88fd6c93aab5bb2cd0e8730376db28f52 Reviewed-on: https://gem5-review.googlesource.com/c/11106 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Remove CacheSet.hhDaniel R. Carvalho
Replacement policies aren't aware of cache sets and do not organize blocks based on replacement data. Block search is independent of block placement. Besides, indexing policies have their own way of addressing the sets, therefore there is no need to use this class anymore. BlkType has been removed, as it wasn't being used. Change-Id: Ia79c2a491e59f295c8d60a0466c317eb0e2bdab9 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/9782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-10mem-cache: Split Tags for indexing policiesDaniel R. Carvalho
Split indexing functionality from tags, so that code duplication is reduced when adding new classes that use different indexing policies, such as set associative, skewed associative or other hash-based policies. An indexing policy defines the mapping between an address' set and its physical location. For example, a conventional set assoc cache maps an address to all ways in a set using an immutable function, that is, a set x is always mapped to set x. However, skewed assoc caches map an address to a different set for each way, using a skewing function. FALRU has been left unmodified as it is a specialization with its own complexity. Change-Id: I0838b41663f21eba0aeab7aeb7839e3703ca3324 Reviewed-on: https://gem5-review.googlesource.com/c/8885 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Use set and way for ReplaceableEntryDaniel R. Carvalho
Replaceable entries belong to table-like structures, and therefore they should be indexable by combining a row and a column. These, using conventional cache nomenclature translate to sets and ways. Make these entries aware of their sets and ways. The idea is to make indexing policies usable by other table-like structures. In order to do so we move sets and ways to ReplaceableEntry, which will be the common base among table entries. Change-Id: If0e3dacf9ea2f523af9cface067469ccecf82648 Reviewed-on: https://gem5-review.googlesource.com/c/12764 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Use possible locations to find blockDaniel R. Carvalho
Use possible locations to find block to make it placement policy independent. Change-Id: I4c9d9e1e1ff91ce12e85ca1970f927d8f4f5a93b Reviewed-on: https://gem5-review.googlesource.com/c/8884 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Create tags initialization functionDaniel R. Carvalho
Having the blocks initialized in the constructor makes it harder to apply inheritance in the tags classes. This patch decouples the block initialization functionality from the constructor by using an init() function. It also sets the parent cache. Change-Id: I0da7fdaae492b1177c7cc3bda8639f79921fbbeb Reviewed-on: https://gem5-review.googlesource.com/c/11509 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Remove Packet dependency in TagsDaniel R. Carvalho
Decouple Tags from Packets, only extracting the necessary functionality for block insertion. As a side effect, create a new function to update common insertion statistics. Change-Id: I5c58f7c17de3255beee531f72a3fd25a30d74c90 Reviewed-on: https://gem5-review.googlesource.com/c/11098 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-05mem-cache: Fix FALRU hash invalidationDaniel R. Carvalho
The block was being invalidated before the hash could erase its entry, therefore it was using invalid values (tag was being assigned MaxAddr and the secure bit was reset). This change reorders the calls, so that the appropriate hash entry is erased. Change-Id: I161463df0f8f5220179bc68d7be12051e5390d01 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13210 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-05mem-cache: Make checking function const in FALRUDaniel R. Carvalho
The checking function should not be able to modify either the head and tail pointers nor should it modify its class. Change-Id: I2ad495f0c8c6b778d48512143e94b4c9a353f22e Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13209 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-05mem-cache: Make boundaries in FALRU an STL containerDaniel R. Carvalho
Turn the dynamically allocated array of pointers "boundaries" into a STL vector. Change-Id: I3409898473b155f69b4c6e038eba2dffb5b09380 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13208 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-05mem-cache: Fix FALRU inCachesMask initializationDaniel R. Carvalho
inCachesMask is not being initialized, which triggers an assertion on insertion. Fix this by implementing a default constructor for the FALRUBlk. Change-Id: I587cf5e0191c4587d938e6ab6036ec1b32f37793 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13207 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-24mem-ruby: Fix a bug in MessageBuffer randomizationXianwei Zhang
In the previous implementation, messages are randomly inserted with delays only if both RubySystem and MessageBuffer randomization flags are set true. However, to find race conditions and cover more slicc transitions, ruby random testers rely on setting RubySystem flag to turn on randomization on all message buffers. As a fix, this patch enables a message buffer to have randomization when either RubySystem or its own flag is set. Change-Id: I1e076908ff07e5846ebad4f4fc1c8f28d40bbfd4 Reviewed-on: https://gem5-review.googlesource.com/12784 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-19mem-cache: Fix non-bijective function in Skewed cachesDaniel R. Carvalho
The hash() function must be bijective for the skewed caches to work, however when the hashing is done on top of a one-bit address, the MSB and LSB refer to the same bit, and therefore their xor will always be zero. This patch adds a fatal error to not allow the user to set an invalid value for the number of sets that would generate that bug. As a side note, the missing header for the bitfields functions has been added. Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021 Reviewed-on: https://gem5-review.googlesource.com/12724 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-17mem: Implement QoS Proportional Fair policyGiacomo Travaglini
Providing a configurable fair scheduling policy based on utilization; utilization is directly proportional to a score which is inversely proportional to the QoS priority. It is meant to avoid starvation of low priority packets. Users can tune the policy by adjusting the weight parameter (weight of the following formula) new_score = ((1.0 - weight) * old_score) + (weight * served_bytes) Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12359 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13mem-cache: Fix bug in handleAtomicReqMissNikos Nikoleris
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug where if an atomic request that fills in using the tempBlock it will not evict it when it finishes handling the request as it should. This triggers an assertion. This change fixes this bug. Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12644 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-07mem: Make DRAMCtrl a QoS-aware Memory ControllerMatteo Andreozzi
This patch is turning DRAMCtrl a QoS-aware Memory Controller with "no policy" as a default policy. Change-Id: I48163da8c8208498cf0398b07094cb840272507f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11973 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-07mem: Implement base QoS Policies.Giacomo Travaglini
This patch implements a base fixed priority policy and an ideal turnaround policy for the QoS memory controller. Change-Id: I38ce16f845fc0ec86d6fc4cc5dc5406f213a465e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11972 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-07mem: Add a simple QoS-aware Memory ControllerMatteo Andreozzi
This patch implements QoSMemorySink: a simple generic QoS-aware memory controller which inherits from QoS::MemCtrl. Change-Id: I537a4e2d4cb8f54fa0002eb088b2c6957afb9973 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11971 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Matthew Poremba <porembam@gmail.com>
2018-09-07mem: Add a QoS-aware Memory Controller typeMatteo Andreozzi
This is the implementation of QoS algorithms support for gem5 memory objects. This change-list provides a framework for specifying QoS algorithm which can be used to prioritise service to specific masters in the memory controller. The QoS support implemented here is designed to be extendable so that new QoS algorithms can be easily plugged into the memory controller as "QoS Policies". Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11970 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-07mem-cache: Create Skewed Assoc placement policyDaniel R. Carvalho
Create a class that implements the skewed associative placement policy. It uses the hash function and expansions of the skewing functions described in "Skewed-Associative caches", by Seznec. Only 8 skewing functions are implemented, and therefore if more are needed a hash function will be recursively applied on top of the output of one of these functions to generate different values. This is not optimal, and if more functions are needed it might be more effective to implement them. Change-Id: Ibc77edffd8128114a8b200cec5d8deedfb5105cb Reviewed-on: https://gem5-review.googlesource.com/8886 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-08-22mem: Add StreamID and SubstreamIDStanislaw Czerniawski
This patch adds StreamID and SubstreamID to Request. These fields can be used by a SMMU/IOMMU model to pick up the correct translation context for each request and they correspond to an ASID in a device. For this reason they have been merged together with the request asid in a union, so that a cpu will set the asid and a device will set the Stream and Substream ID. Change-Id: Iac2b5a1ba9c6598ee7635c30845dc68ba6787c34 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12187 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17scons,ruby: do not generate unnecessary filesBrandon Potter
Do not generate garnet tester file or Ruby debug headers without a Ruby protocol (i.e. PROTOCOL=None). It makes no sense to include these files into the build when there will be no protocol to utilize them. Change-Id: I8db4dd532f60008217a10c88a2e089f85df9d104 Reviewed-on: https://gem5-review.googlesource.com/8381 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-08-17ruby: remove unused code inside '#if 0 ... #endif'Brandon Potter
The commented code contains bitrot. It is not clear how to fix the code so remove it. The code will not compile if the preprocessor defines are removed. The llocker and uulocker variables that are used as indices into the persistent_randomize array are undefined. It's not clear what they should be from the current code. 5ab13e2deb shows when the lines were last modified. The functionality contained in the comments probably have not been used since that time. (This is an example of why one should never add commented code that is enabled by removing defines. The code rots and sits in the source forever.) Change-Id: I3e0e7c9afc0b6088130e6f319075809fb6f16e5a Reviewed-on: https://gem5-review.googlesource.com/8481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-25mem-cache: TempCacheBlk allocates and destroys its own dataRobert Kovacsics
This change is because I want to make CacheBlk::data private, so that I can track all the places which write to it. But to keep that commit smaller (it is pretty big, because of all the places which might change it), I have split this into a commit of its own. Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea Reviewed-on: https://gem5-review.googlesource.com/11829 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-07-23mem: Rename Packet::checkFunctional to trySatisfyFunctionalRobert Kovacsics
Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-20mem: Removed "using namespace std;" from src/mem/packet.ccRobert Kovacsics
To avoid unintentional variable capture, all std calls must be prefixed. These are the identifiers which are in the std namespace (according to https://en.cppreference.com/w/cpp/symbol_index), but that will remain unprefixed with this change: int8_t int16_t int32_t int64_t uint8_t uint16_t uint32_t uint64_t The (u)int types are included from the packet header file, which includes <inttypes.h>, where they occur in the global namespace. They are in the std namespace in <cinttypes>/<cstdint>. There is an occurrence of "set" in this file, which is "Packet::set" and not "std::set", so it is not prefixed with the std namespace Change-Id: I7f6c0b61b09658e224fe31a9f73150b81861d6f8 Reviewed-on: https://gem5-review.googlesource.com/11809 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-19mem: Fix off-by-one error in checkFunctional, and simplify itRobert Kovacsics
There was an off-by-one error in the isRead() case, as `val_end` and `func_end` pointed to the last byte to write to (not one past the last byte), and thus `*_end - *_start` was not the length of the data to memcpy. This was correct in the case of val_start >= func_start && val_end <= func_end where `overlap_size = size`, but if it were (as the other cases suggest) `overlap_size = val_end - val_start`, then it would also be off by one. Also, the isWrite() case catered for this. I simplified the four ifs into one case which uses min/max (this is how I spotted the inconsistency). Change-Id: Ib5c5da084652e752f6baf1eec56b51b4f0f5c95c Reviewed-on: https://gem5-review.googlesource.com/11750 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-07-19mem-cache: Typo in comment: 'proceed' -> 'precede'Robert Kovacsics
The writebacks happen before anything below, not after. Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741 Reviewed-on: https://gem5-review.googlesource.com/11749 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-28mem: Add a memory delay simulatorAndreas Sandberg
Add a memory system component that delays traffic. The base functionality to delay packets is implemented in the abstract MemDelay class. This class exposes three methods that control packet delays: * delayReq(pkt) * delayResp(pkt) * delaySnoopResp(pkt) These methods should be specialized to implement delays for specific packet types. The class SimpleMemDelay uses the MemDelay base class to implement constant delays for read/write requests and responses. The intention is that these classes can be used for rapid prototyping of components that add a small fixed delay and the same throughput as the interconnect. I.e., any buffering done in the base class will be small and proportional to the introduced delay. Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11521 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-22mem-cache: Promote deferred targets on cache clean responsesNikos Nikoleris
While a cache clean operation is pending, all requests to the corresponding block get deferred. When the response of a cache clean operation is received, if the block is present and the response is not invalidating, we can service all deferred targets that didn't require writable. This change implements this functionality. Change-Id: Ief47e74d07749a6a9736ab450eb46eefa53464a2 Reviewed-on: https://gem5-review.googlesource.com/11018 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Promote targets that don't require writableNikos Nikoleris
Until now, all deferred targets of an MSHR would be promoted together as soon as the targets were serviced. Due to the way we handle cache clean operations we might need to promote only deferred targets that don't require writable, leaving some targets as deferred. This change adds support for this selective promotion. Change-Id: I502e523dc9adbaf394955cbacea8286ab6a9b6bc Reviewed-on: https://gem5-review.googlesource.com/11017 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Fix promoting of targets that need writableNikos Nikoleris
There are cases where a request which does not need a writable copy gets an response upgraded reponse and fills in a writable copy. When this happens, we promote deferred MSHR targets that were deferred because they needed a writable copy to service them immediately. Previously, we would uncoditionally promote deferred targets. Since the deferred targets might contain a cache invalidation operation, we have to make sure that any targets following the cache invalidation is not promoted. Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a Reviewed-on: https://gem5-review.googlesource.com/11016 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Selectively clear downstream pendingNikos Nikoleris
Until now, all deferred targets of an MSHR would be promoted together as soon as the targets were serviced. When we promote deferred targets we also clear the downstreamPending flag. Due to the way we handle cache clean operations we might need to promote only deferred targets that don't require writable, leaving some targets as deferred. To allow for partial target promotion, this change adds support for clearing the downstreamPending only for a subset of a TargetsList. Change-Id: Id06953643ba9a975ebacc76ac10215441e264e74 Reviewed-on: https://gem5-review.googlesource.com/11015 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-20mem-cache: Fix TempCacheBlock insertJason Lowe-Power
TempCacheBlock insert() had a different signature than the parent class which caused an error on clang. This matches the signature with default zero values. Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11349 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19mem: Use address range to find the right physical addressNikos Nikoleris
Previously, we used the start address to determine the right physical memory while servicing memory requests. This change uses the full address range to correctly determine the right physical memory and expose bugs where requests might not fully map to a single physical memory. Change-Id: I183d7552918106000f917a62ceb877511ff0ff71 Reviewed-on: https://gem5-review.googlesource.com/11118 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19mem: Use address range to find the destination port in the xbarNikos Nikoleris
Previously the xbar used the start address to lookup the port map and determine the right destination of an incoming packet. This change uses the full address range to correctly determine the right master. Change-Id: I5118712c43ae65aba64e71bf030bca5c99770bdd Reviewed-on: https://gem5-review.googlesource.com/11117 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19mem: Use the caching in the AddrRangeMap class in PhysicalMemoryGabe Black
Use it instead of custom implemented caching. Change-Id: Ie21012a77a3cb6ce57f34f879fa391678913896a Reviewed-on: https://gem5-review.googlesource.com/5244 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19mem: Use the caching built into AddrRangeMap in the xbarGabe Black
Use that instead of caching built into the crossbar. Change-Id: If5a5355a0a1a6e532b14efc88a319de4c023f8c1 Reviewed-on: https://gem5-review.googlesource.com/5243 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19base, mem: Disambiguate if an addr range is contained or overlapsNikos Nikoleris
We need to determined whether an address range is fully contained or it overlaps with an address range in the address range in the mmap. As an example, we use address range maps to associate ports to address ranges and we determine which port we will forward the request based on which address range contains the addresses accessed by the request. We also need to make sure that when we add a new port to the address range map, its address range does not overlap with any of the existing ports. This patch splits the function find() into two functions contains() and intersects() to implement this distinct functionality. It also changes the xbar and the physical memory to use the right function. Change-Id: If3fd3f774a16b27db2df76dc04f1d61824938008 Reviewed-on: https://gem5-review.googlesource.com/11115 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19mem-cache: Fix support for secure blocks in the FALRU cacheNikos Nikoleris
Fully associative caches use an unordered map to enable efficient lookups of existing blocks. Previously this map was indexed using the tag of the block. Security extentions allow secure and non secure versions of a block with the same tag to co-exist in the cache. This patch amends the block map to allow correct lookups for FALRU caches. Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556 Reviewed-on: https://gem5-review.googlesource.com/11309 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-15mem-cache: Initialize CacheBlk data pointerDaniel R. Carvalho
Initialize CacheBlk's data pointer as a nullptr. Change-Id: Ice85b4b11495cad4b0a160ccb9efe1be673e57e2 Reviewed-on: https://gem5-review.googlesource.com/11097 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-15mem-cache: Forward declare ReplaceableEntryDaniel R. Carvalho
Forward declare ReplaceableEntry where in classes where pointers to it are used. Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60 Reviewed-on: https://gem5-review.googlesource.com/11096 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-14base,mem: Support AtomicOpFunctor in the classic memory systemTuan Ta
AtomicOpFunctor can be used to implement atomic memory operations. AtomicOpFunctor is captured inside a memory request and executed directly in the memory hierarchy in a single step. This patch enables AtomicOpFunctor pointers to be included in a memory request and executed in a single step in the classic cache system. This patch also makes the copy constructor of Request class do a deep copy of AtomicOpFunctor object. This prevents a copy of a Request object from accessing a deleted AtomicOpFunctor object. Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37 Reviewed-on: https://gem5-review.googlesource.com/8185 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-14ruby: Revamp standalone SLICC scriptJason Lowe-Power
There was some bitrot in the standalone SLICC script (util/slicc and src/mem/slicc/main.py). Fix the changes to the SLICC interface and also add some better documentation. Change-Id: I91c0ec78d5072fba83edf32b661ae67967af7822 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/10561 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Remove unnecessary cast in SectorTags::findVictimNikos Nikoleris
Removes an uneccessary cast that also caused an unused variable error (due to -Werror) when compiling .fast targets. Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980 Reviewed-on: https://gem5-review.googlesource.com/11119 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Insert on block allocationDaniel R. Carvalho
When a block is being replaced in an allocation, if successfull, the block will be inserted. Therefore we move the insertion functionality to allocateBlock(). allocateBlock's signature has been modified to allow this modification. Change-Id: I60d17a83ff4f3021fdc976378868ccde6c7507bc Reviewed-on: https://gem5-review.googlesource.com/10812 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Make packet const in insertBlockDaniel R. Carvalho
The packet should not be modified within insertBlock. Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a Reviewed-on: https://gem5-review.googlesource.com/10811 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 06:48:44 +0000