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mem
Age
Commit message (
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Author
2015-01-20
mem: Move DRAM interleaving check to init
Andreas Hansson
2014-12-23
mem: Change prefetcher to use random_mt
Mitch Hayenga
2014-12-23
mem: Hide WriteInvalidate requests from prefetchers
Curtis Dunham
2014-12-23
mem: Fix event scheduling issue for prefetches
Mitch Hayenga
2014-12-23
mem: Fix bug relating to writebacks and prefetches
Mitch Hayenga
2014-12-23
mem: Rework the structuring of the prefetchers
Mitch Hayenga
2014-12-23
mem: Add parameter to reserve MSHR entries for demand access
Mitch Hayenga
2014-12-23
config: Expose the DRAM ranks as a command-line option
Andreas Hansson
2014-12-23
mem: Ensure DRAM controller is idle when in atomic mode
Andreas Hansson
2014-12-23
mem: Add rank-wise refresh to the DRAM controller
Omar Naji
2014-12-23
mem: Fix a bug in the DRAM controller arbitration
Omar Naji
2014-12-23
mem: Add stack distance statistics to the CommMonitor
Kanishk Sugand
2014-12-23
mem: Add a stack distance calculator
Kanishk Sugand
2014-12-23
mem: Add MemChecker and MemCheckerMonitor
Marco Elver
2014-12-02
mem: Support WriteInvalidate (again)
Curtis Dunham
2014-12-02
mem: Remove WriteInvalidate support
Curtis Dunham
2014-12-02
mem: Relax packet src/dest check and shift onus to crossbar
Andreas Hansson
2014-12-02
mem: Clean up packet data allocation
Andreas Hansson
2014-12-02
mem: Cleanup Packet::checkFunctional and hasData usage
Andreas Hansson
2014-12-02
mem: Make the requests carried by packets const
Andreas Hansson
2014-12-02
mem: Make Request getters const
Andreas Hansson
2014-12-02
mem: Add checks and explanation for assertMemInhibit usage
Andreas Hansson
2014-12-02
mem: Assume all dynamic packet data is array allocated
Andreas Hansson
2014-12-02
mem: Remove redundant Packet::allocate calls
Andreas Hansson
2014-12-02
mem: Use const pointers for port proxy write functions
Andreas Hansson
2014-12-02
mem: Add const getters for write packet data
Andreas Hansson
2014-12-02
mem: Remove null-check bypassing in Packet::getPtr
Andreas Hansson
2014-12-02
mem: Add a GDDR5 DRAM config
Omar Naji
2014-11-24
misc: Another round of static analysis fixups
Andreas Hansson
2014-11-23
mem: Page Table map api modification
Alexandru Dutu
2014-11-23
mem: Multi Level Page Table bug fix
Alexandru Dutu
2014-11-23
mem: Page Table long lines
Alexandru Dutu
2014-11-14
mem: Clarify unit of DRAM controller buffer size
Andreas Hansson
2014-11-12
mem: Delete unused variable in Garnet NetworkLink
Mitch Hayenga
2014-11-06
ruby: provide a backing store
Nilay Vaish
2014-11-06
ruby: interface with classic memory controller
Nilay Vaish
2014-11-06
ruby: remove the function functionalReadBuffers()
Nilay Vaish
2014-11-06
ruby: coherence protocols: remove data block from dirctory entry
Nilay Vaish
2014-11-06
ruby: slicc: allow adding a bool to an int, like C++.
Nilay Vaish
2014-11-06
ruby: remove sparse memory.
Nilay Vaish
2014-11-06
ruby: single physical memory in fs mode
Nilay Vaish
2014-11-06
ruby: dma sequencer: remove RubyPort as parent class
Nilay Vaish
2014-10-29
arm, mem: Fix drain bug and provide drain prints for more components.
Ali Saidi
2014-10-21
mem: don't inhibit WriteInv's or defer snoops on their MSHRs
Curtis Dunham
2014-10-29
mem: have WriteInvalidate obsolete MSHRs
Curtis Dunham
2014-10-20
mem: Fix DRAM activationlLimit bug
Omar Naji
2014-10-20
mem: Add DRAM device size and check against config
Omar Naji
2014-10-16
mem: Modernise PhysicalMemory with C++11 features
Andreas Hansson
2014-10-16
misc: Move AddrRangeList from port.hh to addr_range.hh
Andreas Hansson
2014-10-16
mem: Add ExternalMaster and ExternalSlave ports
Andrew Bardsley
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