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path: root/src/mem
AgeCommit message (Expand)Author
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
2014-01-28mem: Fixes a bug in simple_dram write mergingAmin Farmahini
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24mem: Add flag to request if it was generated by a page table walkGiacomo Gabrielli
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24Cache: Collect very basic stats on tag and data accessesTimothy M. Jones
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-17ruby: remove unused label no_vectorNilay Vaish
2014-01-10ruby: move all statistics to stats.txt, eliminate ruby.statsNilay Vaish
2014-01-09ruby: fix bug introduced to revision 8523754f8885Nilay Vaish
2014-01-08ruby: slicc: remove variable 'addr' used in calls to doTransitionNilay Vaish
2014-01-04ruby: add a three level MESI protocol.Nilay Vaish
2014-01-04ruby: rename MESI_CMP_directory to MESI_Two_LevelNilay Vaish
2014-01-04ruby: add support for clustersNilay Vaish
2014-01-04ruby: some small changesNilay Vaish
2013-12-26ruby: fix bugs in mesi cmp directory protocolNilay Vaish
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
2013-12-20ruby: declare variables to be unsigned in Address.hhNilay Vaish
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
2013-11-01mem: Unify request selection for read and write queuesNeha Agarwal
2013-11-01mem: Add a simple adaptive version of the open-page policyAndreas Hansson
2013-11-01mem: Just-in-time write scheduling in DRAM controllerNeha Agarwal
2013-11-01mem: Add tRRD as a timing parameter for the DRAM controllerAndreas Hansson
2013-11-01mem: Less conservative tRAS in DRAM configurationsAndreas Hansson
2013-11-01mem: Make tXAW enforcement less conservative and per rankAni Udipi
2013-11-01mem: Fix for 100% write threshold in DRAM controllerNeha Agarwal
2013-11-01mem: Pick the next DRAM request based on bank availabilityAndreas Hansson
2013-11-01mem: Use the same timing calculation for DRAM read and writeAni Udipi
2013-11-01mem: Fix DRAM bank occupancy for streaming accessAni Udipi
2013-11-01mem: Schedule time for DRAM event taking tRAS into accountAni Udipi
2013-11-01mem: Add tRAS parameter to the DRAM controller modelAni Udipi
2013-10-31mem: Add "const" attribute to Packet gettersStephan Diestelhorst
2013-10-31mem: Add privilege info to request classPrakash Ramrakhyani
2013-10-30ruby: set SenderMachine in messages of MOESI_CMP_directoryLluc Alvarez
2013-10-30ruby: Fixed a deadlock when restoring a checkpoint with garnetEmilio Castillo
2013-10-17mem: De-virtualise interfaces in the CoherentBusStephan Diestelhorst
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17mem: Add PortID to QueuedMasterPort constructorSascha Bischoff
2013-10-17mem: Make MemoryAccess flag more verboseAli Saidi
2013-10-15ruby: eliminate non-determinism from ruby.stats outputSteve Reinhardt
2013-10-15mem: Rename the ASI_BITS flag field in RequestAndreas Sandberg
2013-10-15mem: Use a flag instead of address bit 63 for generic IPRsAndreas Sandberg
2013-09-18mem: Fix scheduling bug in SimpleMemoryAndreas Hansson