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2019-07-06mem-ruby: Remove Bloom Filters' ruby dependencyDaniel R. Carvalho
Substitute the common ruby header by base's bitfield to eliminate all ruby dependency in Bloom Filters. As a side note, BulkBloomFilter now assumes addresses are 64 bit long. Change-Id: Ibdb1f926ddcc06c848851c1e6a34863541808360 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18738 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-06mem-ruby: Parameterize block size in Bloom FiltersDaniel R. Carvalho
Substitute all occurrences of Ruby's block size by a Python configurable offset. Change-Id: If4913e842921447deda943b0482fb0c78a44c275 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18737 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-06mem-ruby: Make Bloom Filters SimObjectsDaniel R. Carvalho
Make all bloom filters SimObjects. Change-Id: I586293cdfb559361cb868b3198368e8b9b193356 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18736 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Generalize use of bloom filters' isSetDaniel R. Carvalho
In general the corresponding entries of an address are considered to be set when the sum of all of them reach their maximum value (i.e., they are all set), so generalize that into the base class. Change-Id: If50b8c56065ad339b4ff2322ddc3c077a3bfc518 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18735 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Cleanup filtersDaniel R. Carvalho
Renamed member variables to comply with general naming conventional outside of the ruby folder so that the filters can be moved out. Moved code to base to reduce code duplication. Renamed the private get_index functions to hash, to make their functionality explicit. Change-Id: Ic6519cfc5e09ea95bc502a29b27f750f04eda754 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18734 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Fix MultiGrainBloomFilter total count calculationDaniel R. Carvalho
Previous value was always 0, and was never incrementing. The total count should take into account the value stored in the entry. Change-Id: I93813e3f388198967b30cf11848a8a8c3a7b91f4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18733 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Remove index based functions in bloom filtersDaniel R. Carvalho
Most of the index based functions were not implemented, and a user is more likely to be interested in checking the filter contents based on an address than an index. As a side effect, the Bulk's hash function became unused, and according to the paper permute() was doing more than just permuting, so it was renamed. Change-Id: I6423a2565a082fee2e7f11fa489a11f253064d99 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18732 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Remove Bloom Filter's print()Daniel R. Carvalho
Print was unused. As a side effect 'using namespace std' is no longer needed. Change-Id: Ief10cba1a11dfdd4edb7464eb9291fc83d6668cd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18731 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Standardize Bloom Filter deletion supportDaniel R. Carvalho
Standard Bloom Filters do not support element deletion by default, however some variants do. Allow calling the unset function with all filters, and do nothing by default. Change-Id: Icf4b0f8b997c4c70fa714b2576474810275db78b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18730 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-07-06mem-ruby: Bloom filters - Remove in/decrementDaniel R. Carvalho
Increment and decrement were functions created to supply the different naming convention used by the counting bloom filter. They were removed, and the set and unset functions were used in their place instead, as in the other filters. Change-Id: I45732bdfa3083add0a975f374a0f3560003e9d09 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18729 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-06-06mem: Option to toggle DRAM low-power statesMatthew Poremba
Adding an option to enable DRAM low-power states. The low power states can have a significant impact on application performance (sim_ticks) on the order of 2-3x, especially for compute-gpu apps. The options allows for it to easily be enabled/disabled to compare performance numbers. The option is disabled by default. Change-Id: Ib9bddbb792a1a6a4afb5339003472ff8f00a5859 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18548 Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-05mem-ruby: Enable set size increaseJohn Alsop
Add NUMBER_BITS_PER_SET environment variable to control the size of the bitmask in Set.hh (default=64). Necessary for configs which require >64 instances of a given machine type. This can be set in the build_opts file, e.g. by adding the following line: NUMBER_BITS_PER_SET = <number> Change-Id: I314a3cadca8ce975fcf4a60d9022494751688e88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18968 Reviewed-by: Tiago Mück <tiago.muck@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-04Revert "mem-cache: Remove writebacks packet list"Daniel Carvalho
This reverts commit bf0a722acdd8247602e83720a5f81a0b69c76250. Reason for revert: This patch introduces a bug: The problem here is that the insertion of block A may cause the eviction of block B, which on the lower level may cause the eviction of block A. Since A is not marked as present yet, A is "safely" removed from the snoop filter However, by reverting it, using atomic and a Tags sub-class that can generate multiple evictions at once becomes broken when using Atomic mode and shall be fixed in a future patch. Change-Id: I5b27e54b54ae5b50255588835c1a2ebf3015f002 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19088 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-30mem: Remove the now unused Copy* methods from the FS port proxy.Gabe Black
Change-Id: Ie433a9e4c9ee748911060eb7b1b47e617aa297a6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18576 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29mem-cache: Accuracy-based rate control for prefetchersJavier Bueno
Added a mechanism to control the number of prefetches generated based in the effectiveness of the prefetches generated so far. Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29mem-cache: Support for page crossing prefetchesJavier Bueno
Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29mem: Add a readString method to the PortProxy which takes a char *.Gabe Black
This version takes a char * instead of an std::string &, and a maximum length to fill in like strncpy. This is intended to be a replacement for the CopyStringOut function. Change-Id: Ib661924a3fa7e05761d572ffecbe2c0cc8659d48 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18574 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29mem: Use a const T & in write<> to avoid an unnecessary copy.Gabe Black
If the type T is complex/large, the it makes sense to access it in place and not copy it and then not modify it. Change-Id: Idd24be4fbba636375637ff72b1ba5ee32eb76215 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18573 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29mem, arm: Replace the pointer type in PortProxy with void *.Gabe Black
The void * type is for pointers which point to an unknown type. We should use that when handling anonymous buffers in the PortProxy functions, instead of uint8_t * which points to bytes. Importantly, C/C++ doesn't require you to do any casting to turn an arbitrary pointer type into a void *. This will get rid of lots of tedious, verbose casting throughout the code base. Change-Id: Id1adecc283c866d8e24524efd64f37b079088bd9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18571 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29mem, arm: Move some helper methods into the base PortProxy class.Gabe Black
These were originally in the SETranslatingPortProxy class, but they're not specific to SE mode in any way and are an unnecessary divergence between the SE and FS mode translating port proxies. Change-Id: I8cb77531cc287bd15b2386410ffa7b43cdfa67d0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18570 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-29arm, mem: Move the SecurePortProxy subclass into it's own file.Gabe Black
The idea of a "secure" memory area/access is specific to ARM and shouldn't be in the common mem directory, although it's built in to the generic memory protocol at this point. Regardless, it should minimially be in its own file like the virtual and physical port proxy classes are. Change-Id: I140d4566ee2deded784adb04bcf6f11755a85c0c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18569 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28mem: Parameterize coherent xbar sanity checksTiago Muck
Parameters can be used to change coherent xbar limits for the routing table and outstanding snoops. We need the ability to tweak these values as the current defaults may be violated in simulations with large core counts. Change-Id: Idb64b8c105683d02d8beba5bce13b815181ba824 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18789 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-28mem: Snoop filter support for large systemsTiago Muck
Changed SnoopMask to use std::bitset instead of uint64 so we can simulate larger systems without having to workaround limitations on the number of ports. No noticeable performance drop was observed after this change. The size of the bitset is currently set to 256 which should fit most needs. Change-Id: I216882300500e2dcb789889756e73a1033271621 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18791 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-22mem: Add invalid context id check on LLSC checksTiago Muck
If the request's address is in the LLSC list, its context Id was being fetched unconditionally, which could cause the assert at Request::contextId() to fail. Change-Id: Iae9791f81c8fe9a7fcd842cd8ab7db18f34f2808 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18792 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20mem-cache: Add multi-prefetcher adaptorAndreas Sandberg
This patch adds a meta-prefetcher that enables gem5's cache models to connect to multiple prefetchers. Sub-prefetchers still use the probes-based interface and training can be controlled independently. However, when the cache requests a prefetch packet, the adaptor traverses the priority list of prefetchers and uses the first prefetcher that is able to generate a prefetch. Kudos to Mitch Hayenga for the original version of this patch. Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-14mem-ruby: MOESI_CMP_dir cleanupTiago Muck
Removed unused states and actions Change-Id: I3dc684c78d4b92d219e71522ddb706a13f9874d1 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18415 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Cache latencies for MOESI_CMP_dirTiago Muck
Modified both L1 and L2 controllers to take into account the cache latency parameters. Default values in the configuration script updated as well. Change-Id: I72bb8dd29ee0b02da06e1addf13b266fe4d1e979 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18414 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Hit latencies defined by the controllersTiago Muck
Removed the icache/dcache hit latency parameters from the Sequencer. They were replaced by the mandatory queue enqueue latency that is now defined by the top-level cache controller. By default, the latency is defined by the mandatory_queue_latency parameter. When the latency depends on specific protocol states or on the request type, the protocol may override the mandatoryQueueLatency function. Change-Id: I72e57a7ea49501ef81dc7f591bef14134274647c Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18413 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Do not change blocked msg enqueue infoTiago Muck
Updating the message counter and enqueue times when adding blocked messages back to the queue does not make a lot of sense since these messages are not new arrivals. More importantly, this may lead to starvation. See the scenario below: 1) Request A for a blocked line X arrives 2) A is handled; X is blocked so A is stalled 3) Request B for X arrives; Reponse for X arrives 4) Response is handled; X unblocked; A added back to the request queue 5) B is handled ahead of A (since A's arrival was updated); X may become blocked again If new requests keep comming for X, A may will be stalled forever. Change-Id: Icad79f3f716a870e91cb3455437b8b3c35f130ac Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18412 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Unique ranks for MOESI_CMP_dir in portsTiago Muck
Setting different values for the rank parameter for all inputs ports. If left unset, it defaults to 0. This may cause issues since the rank is used as an index in the controller's list of stalled buffers. Change-Id: Ie8ff660b7450df959292311040aebf802657efcf Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Change MOESI_CMP_Dir L2 addressingTiago Muck
L1 controller selects the L2 to message based on the assigned address ranges instead of explicitly interleaving bits in the L1 controller. This simplifies the L1 controller implementation a bit and allows for more flexibility when changing the address->controller mapping. Change-Id: Ie67999bb977566939432a5045f65dbd2da81816a Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Fix MOESI_CMP_dir debug msgTiago Muck
Change-Id: I3fd32bd2e81dbf9a8ea49a43727564b8a9d64767 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18409 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-ruby: Prevent response stalls on MOESI_CMP_directoryTiago Muck
When a message triggers a transition that has actions which allocate TBEs, the generated code automatically includes a check for the TBETable size before executing any action. If the table is full, the transition returns TransitionResult_ResourceStall and no more messages from the buffer are handled (until the next cycle). This behavior may lead to deadlocks in the MOESI_CMP_directory protocol since events triggered by the response queue may allocate TBEs (e.g. L2 replacements triggered by the response queue). If the table is full, the queue is stalled preventing other responses from freeing TBEs. This patch fixes this by handling WRITEBACK_DIRTY_DATA/CLEAN_DATA messages as requests and WB_ACK/WB_NACK as responses. All controllers are changed to work with the new types. With this fix, responses are always handled first in all controllers, and no response triggers TBE allocations. Change-Id: I377c0ec4f06d528e9f0541daf3dcc621184f2524 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18408 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-14mem-cache: Use SatCounter for prefetchersDaniel
Many prefetchers re-implement saturating counters with ints. Make them use SatCounters instead. Added missing operators and constructors to SatCounter for that to be possible and their respective tests. Change-Id: I36f10c89c27c9b3d1bf461e9ea546920f6ebb888 Signed-off-by: Daniel <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17995 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-12mem-ruby: Replace string parameter in MultiBitSelBloomFilterDaniel R. Carvalho
Replace string parameter from MultiBitSelBloomFilter's constructor by their tokenized counterparts. Change-Id: I2e3db109dc4814fa0e9c13259f1136a6c4083092 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18728 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
This changeset adds support for partial (or masked) loads/stores, i.e. loads/stores that can disable accesses to individual bytes within the target address range. In addition, this changeset extends the code to crack memory accesses across most CPU models (TimingSimpleCPU still TBD), so that arbitrarily wide memory accesses are supported. These changes are required for supporting ISAs with wide vectors. Additional authors: - Gabor Dozsa <gabor.dozsa@arm.com> - Tiago Muck <tiago.muck@arm.com> Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-09mem-ruby: Fix MOESI_CMP_directory blocked line handlingTiago Muck
Using recycle in the L2 controllers to put messages back into the buffer may lead to starvation when there are many L1 requests for the same line. This can easily trigger the deadlock detection mechanism in configurations with many cores (16+). Replacing recycle by stall_and_wait for L1 requests avoids this issue. wakeUpBuffers calls were added to all transitions from transient to stable states. Change-Id: I28b8aeacc48919ccf38e69653cd9205a4153514b Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17568 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-08mem-cache: Remove writebacks packet listDaniel R. Carvalho
Previously all atomic writebacks concerned a single block, therefore, when a block was evicted, no other block would be pending eviction. With sector tags (and compression), however, a single replacement can generate many evictions. This can cause problems, since a writeback that evicts a block may evict blocks in the lower cache. If one of these conflict with one of the blocks pending eviction in the higher level, the snoop must inform it to the lower level. Since atomic mode does not have a writebuffer, this kind of conflict wouldn't be noticed. Therefore, instead of evicting multiple blocks at once, we do it one by one. Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18209 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Handle data expansionDaniel R. Carvalho
When a block in compressed form is overwriten, it may change its size. If the new compressed size is bigger, and the total size becomes bigger than the block size, one or more blocks will have to be evicted. This is called data expansion, or fat writes. This change assumes that a first level cache cannot have a compressor, since otherwise data expansion should have been handled for atomic operations and writes. As such, data expansions should only be seen on writebacks. As writebacks are forwarded to the next level when failed, there should be no data expansions when servicing misses either. This patch adds the functionality to handle data expansions by evicting the co-allocated blocks to make room for an expanded block. Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12087 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-08mem-cache: Add co-allocation function to compressed tagsDaniel R. Carvalho
Implement a co-allocation function in compressed tags, so that compressed blocks can be co-allocated in a superblock. Co-allocation is possible when compression ratio (CR) blocks that share a superblock tag can be compressed to up to (100/CR)% of their size. Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression and decompression callsDaniel R. Carvalho
Add a compressor to the base cache class and compress within block allocation and decompress on writebacks. This change does not implement data expansion (fat writes) yet, nor it adds the compression latency to the block write time. Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11410 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create BDI CompressorDaniel R. Carvalho
Implement Base-Delta-Immediate compression, as described in 'Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches' Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression statsDaniel R. Carvalho
Add compression statistics to the compressors. It tracks the number of blocks that can fit into a certain power of two size, and the number of decompressions. For example, if a block is compressed to 100 bits, it will belong to the 128-bits compression size. Although it could also fit bigger sizes, they are not taken into account for the stats (i.e., the 100-bit compression will fit only the 128-bits size, not 256 or higher). We save stats for compressions that fail (i.e., compressed size is bigger than original cache line size). Change-Id: Idab71a40a660e33259908ccd880e42a880b5ee06 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11103 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create cache compressorDaniel R. Carvalho
Create basic template for cache compressors. A basic compressor must implement a compression and a decompression method. Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add block size to findVictimDaniel R. Carvalho
Add block size to findVictim. For standard caches it will not be used. Compressed caches, however, need to know the size of the compressed block to decide whether a block is co-allocatable or not. Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Add compression data to CompressionBlkDaniel R. Carvalho
Add a compression bit, decompression latency and compressed block size and their respective getters and setters. Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-08mem-cache: Create CacheComp debug flagDaniel R. Carvalho
Create a debug flag for cache compression. Change-Id: Id4b8e86d658d3aa550906ee0f8da3b54f4cdab7d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11104 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-08mem-cache: Stub compression frameworkDaniel R. Carvalho
Create a stub of a compression framework where we can have multiple data blocks per tag entry. Only consecutive blocks can share a tag as of now. For each tag entry there can be multiple data blocks. We have the same number of tags a conventional cache would have, but we instantiate the maximum number of data blocks (according to the compression ratio) per tag, to virtually implement compression without increasing the complexity of the simulator. Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-03mem-cache: Mark block as dirty after a SWPrefetchEXRespNikos Nikoleris
This is a workaround for a bug introduced from the change: 59e3585a8 arch-arm: We add PRFM PST instruction for arm which can cause deadlocks in the memory system. The design of the classic memory system in gem5 makes the folloing two assumptions: * A cache that fetches a block with an intention to modify it, becomes the point of ordering and therefore commits to respond to any snoop requests [1]. * A cache that fetches an exclusive copy of the block, does so with the intention to modify it [2]. Immediately after it receives the block, it will write to it and mark it as dirty. As the point of ordering, it responds to any outstanding snoops. The current implementation of prefetch exclusive request breaks the second assumption. A cache can fetch an exclusive block without an immediate intention to modify it. If the block is not modified, it will not be marked as dirty. However, the cache has committed to respond to outstanding snoops, and if the block is clean it won't. This can result in deadlocks where a snoop gets stuck waiting for responses. One solution (implemented by this patch) is to unconditionally mark the block dirty when filling due to a prefetch exclusive request. This makes the PrefetchExReq behave like a WriteReq. However, as it may mark as dirty a clean block, it creates the requirement for an uncessary WritebackDirty in the future. In practice, this shouldn't be a big problem unless the application is unnecessarily using prefetch exclusive instructions. Other solutions, would require deeper changes to the design of the memory system to handle this properly. [1]: When a cache commits to respond, it "informs" the xbar/PoC (point of coherence) and the other caches of its intention to respond. As a result the request will not be send to the main memory. [2]: In fact the assumption is that in the needsWritable MSHR there is at least one WriteReq before any snoops from other caches. Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17729 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 19:04:17 +0000