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2019-12-12mem: Encapsulate mapping gem5 to host address spaceDaniel R. Carvalho
Create a function to encapsulate mapping an address in gem5's address space to the host's address space. The returned value can be used to access the contents of the given address. As a side effect, make the local variable hostAddr use snake_case to comply with gem5's coding style. Change-Id: I2445d3ab4c7ce5746182b307c26cbafc68aa139c Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22610 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-12mem-cache: Move unused prefetches counter updateDaniel R. Carvalho
The number of unused prefetches should be updated every time a block is invalidated, therefore we move the update to within the corresponding function. Change-Id: If3ac2ea43611525bd3c36d628d88382042fcb7dc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18908 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-12-09mem: Add Request::isMasked to check for byte strobingGiacomo Travaglini
This is trying to overcome the following problem: At the moment a memory request with a non empty byteEnable mask will be considered masking even if all elements in the vector are true. Change-Id: I16ae2c0ea8c3f3370e397bab9d79d6d60c3784bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23284 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-09mem: Add byteEnable copy to Request copy constructorGiacomo Travaglini
Change-Id: Ie97543e62524bb244ae65eef096411af4605c175 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23283 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Avoid hiding a virtual method in the dictionary compressor.Gabe Black
The non-virtual version is later used in overrides of the virtual version whcih takes more arguments. Change-Id: I102d1185c7a616337c2a0429daa998706189292f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23127 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Remove a std::move clang says is unnecessary.Gabe Black
It also says it prevents an optimization. Change-Id: I9c21dc1a0c53cf70cefd1400564de07d1e845a75 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23124 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.Isaac Sánchez Barrera
Members `tc` and `ongoingTranslation` were uninitialized in the constructor for `QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not initialized to `false` by default, some translation requests from queued prefetchers are not properly handled and executions are nondeterministic. Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794 Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22844 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.Isaac Sánchez Barrera
The destructor of `BasePrefetcher::PrefetchInfo` was calling `delete` for a dynamically-allocated array. Changed to `delete[]` to remove potential undefined behaviour. Change-Id: I6f531bfb6fb7108f1d3e743ae0384d80173e15ef Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22843 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-05mem-ruby: Reset Ruby Sequencer Outstanding Requests statsPolydoros Petrakis
Change-Id: I14b106e0eb7abd9c14badeedf35d6d1c9f198f98 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22446 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Modify compressor to appease newer compilersDaniel R. Carvalho
The type of the local unique_ptr variable was different from the return type. In C++11 because of such difference, a copy-ellision would not be possible, and that required the use of a std::move. In C++14 the restriction of same types being required was removed, so std::move would not be needed anymore. With the addition of the -Wredundant-move warning in newer compilers, having the std::move on the return became an issue, breaking compilation. Change-Id: I45d18dfc500bb5db5fe360814feb91853c735a19 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22403 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-11-04mem-cache: Implement a perfect compressorDaniel R. Carvalho
Implement a perfect compressor that always manages to compresses data exactly to its maximum allowed compression ratio. This allows tracking a compression upper bound. Change-Id: Ibc68bf2dc84b75207795d5ba6304b9ed6dbeae8f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21160 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Make BDI a multi compressorDaniel R. Carvalho
BDI is a compressor containing multiple sub-compressors. Change-Id: I98411e2ef9dcc2182801a172dfc59ed7a8ee7dd4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21159 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a multi compressorDaniel R. Carvalho
Implement a compressor that contains multiple sub-compressors and choses the one that provides the best compression results for each compression. Change-Id: I758cf67c84bd85edbea16b2a07b2068b00454461 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21158 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Implement BDI sub-compressorsDaniel R. Carvalho
Implement sub-compressors of BDI as public compressors so that they can be used separately. Change-Id: I710e35f39f4abb82fd02fd33b1b86a3f214c12cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21157 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a repeated values compressorDaniel R. Carvalho
The repeated values compressor can only compress data composed solely repeated instances of the same value. Change-Id: If2c4f47ad4af492d202ec2017e30ba52ee67e307 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21156 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a zero compressorDaniel R. Carvalho
The zero compressor can only compress data composed solely of zero bits. Change-Id: I8b359c03776a8748abd144a178bda944b5a1b766 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21155 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement FPC-D cache compressionDaniel R. Carvalho
Implementation of Frequent Pattern Compression with limited Dictionary support (FPC-D) cache compressor, as described in "Opportunistic Compression for Direct-Mapped DRAM Caches", by Alameldeen et al. Change-Id: I26cc1646f95400b6a006f89754f6b2952f5b4aeb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21154 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-01mem: Delete the packet accessors which use guest endianness.Gabe Black
These accessors create an extra dependency on the guest OS, and can be avoided. Now that all their uses have been removed, they aren't needed any more. Change-Id: I466c07fef99bce2d7964c07a7ac3dd398691378b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13465 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-31mem-cache: Fix missing header in associative setDaniel R. Carvalho
Add missing intmath header to AssociativeSet, so that isPowerOf2 can be used. error: there are no arguments to 'isPowerOf2' that depend on a template parameter, so a declaration of 'isPowerOf2' must be available Change-Id: Ib2b194f9e71284ee439786bdb76d99858e57e2f5 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22444 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-31mem-ruby: Fixed pipeline squashes caused by aliased requestsJoe Gross
This patch was created by Bihn Pham during his internship at AMD. This patch fixes a very significant performance bug when using the O3 CPU model and Ruby. The issue was Ruby returned false when it received a request to the same address that already has an outstanding request or when the memory is blocked. As a result, O3 unnecessary squashed the pipeline and re-executed instructions. This fix merges readRequestTable and writeRequestTable in Sequencer into a single request table that keeps track of all requests and allows multiple outstanding requests to the same address. This prevents O3 from squashing the pipeline. Change-Id: If934d57b4736861e342de0ab18be4feec464273d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21219 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a repeated value pattern to compressorsDaniel R. Carvalho
The repeated value pattern checks if values are composed of multiple instances of the same value. If successful, the bits of the repeated value are included only once in the compressed data. Change-Id: Ia7045b4e33a91fd8d712fe1ca689f7f8cb4e5feb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21153 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Inform unused bits instead of bytes in compressor patternDaniel R. Carvalho
Increase pattern precision by giving the number of unmatched bits instead of bytes. Change-Id: I5efbe9c31672cc973b4c89c741cdc8cc28d26285 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21152 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked const value pattern to compressorsDaniel R. Carvalho
The masked pattern compares values to masked const non-dictionary values to determine whether these match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4c53568694dab916136fe384cb2ee10e554f7136 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21151 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked pattern to compressorsDaniel R. Carvalho
The masked pattern compares masked values to masked dictionary entries to determine whether these values match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4b1c8feb0faa99576382b54a73a20c353f965d2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21150 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add an uncompressed pattern to compressorsDaniel R. Carvalho
The uncompressed pattern always stores the original data, and therefore it is always successful. All of the derived classes of the dictionary compressor must have this pattern as the last pattern of the pattern factory. Change-Id: I2a38fd56630d88ef8b918220dc4c2824a196a8a2 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21149 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Templatize DictionaryCompressorDaniel R. Carvalho
Templatize DictionaryCompressor so that the dictionary entries' sizes can be changed. Change-Id: I3d89e3c692a721cefcd7e3c55d2ccdefa425f614 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21148 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Factor out CPack's dictionary functionalityDaniel R. Carvalho
Factor out dictionary functionality of CPack, so that it can be used easily for other compressors. As a side effect, create an addToDictionary function to allow subclasses to chose how to handle insertion. Change-Id: I02fae4e98b02db5a40467ec470b71020d5e867cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21147 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-10-29mem-cache: Use shouldAllocate() instead of CPack's decompress()Daniel R. Carvalho
Split decompression functionality using the proper function to determine if a dictionary entry should be allocated after decompression or not. Change-Id: I4995304f4c4508c03c9fc1685f04511622969556 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21146 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Limit compression sizeDaniel R. Carvalho
Add a threshold so that if the compressed size is greater than it, the compression is abandoned, and the data is considered uncompressible. Change-Id: Ic416195b06ec440a40263b75bd0f0383cde2ea6a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21144 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Do not try to compress dataless packetsDaniel R. Carvalho
Fix filling blocks so that packets that do not contain data do not generate a compression attempt. This can happen, for example, with invalidation responses, which will trigger a packet data access assertion. Change-Id: I2a1e7983657f6e5e770b148ab62c9de9ac3986ac Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22164 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem: Fix DRAM controller to operate on its own address spaceNikos Nikoleris
Typically, a memory controller is assigned an address range of the form [start, end). This address range might be interleaved and therefore only a non-continuous subset of the addresses in the address range is handed by this controller. Prior to this patch, the DRAM controller was unaware of the interleaving and as a result the address range could affect the mapping of addresses to DRAM ranks, rows and columns. This patch changes the DRAM controller, to transform the input address to a continuous range of the form [0, size). As a result the DRAM controller always operates on a dense and continuous address range regardlesss of the system configuration. Change-Id: I7d273a630928421d1854658c9bb0ab34e9360851 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19328 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Avoid promotion of incompatible deferred targetsNikos Nikoleris
Often a request that hits on an MSHR has to be deferred as it can't be serviced by the current response. For example, a request that requires writable has to be deferred when the response is expected to bring in a read-only copy of the block. However, there are cases where the response, although not expected to do so, brings a writable copy and as a result we also service deferred targets. In such cases, we promote deferred targets up until the first that can't be serviced by the current response (e.g., cache maintainance operation). If the first deferred target is incompatible we don't promote any targets at all. Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22127 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-29mem-cache: Fix MSHR whole line write trackingNikos Nikoleris
The MSHR keeps track of outstanding writes and services them as a whole line write whenever possible. To do this the outstanding writes have to be compatible (e.g., not strictly ordered). Prior to this change, due to this tracking mechanism, the MSHR would not service a WriteLineReq with flags that do not allow merging as a full line write even if it was the first target triggering an assertion. This changeset fixes this bug. Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-18mem: Delete the MessageReq and MessageResp memory commands.Gabe Black
Now that Message*Port is gone, there are no users of these two memory commands. They can now be deleted, simplifying the memory system slightly. Change-Id: If157dade4a3fb2610756c2ee81dc0c3fac670a26 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20824 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-13mem-cache: set the second chance to false when inserting a blockMingyuan
Modify second chance replacement policy so that entries are inserted without a second chance. Previously, the second chance bit was set to true when a cache line was inserted. So the cache line would gain its second chance when inserting. This is wrong because the cache block will only get a second chance when it hits. Here's a quoted citation for the second chance replacement policy: "Whenever the algorithm examines a page entry, it extracts the associated usage bit and enters it into the high-order position of a k-bit shift register after shifting the contents of the register one bit-position lower. Then if the shift register is nonzero, the page is retained; if the shift register is zero, the page is replaced by the new page. In either case the usage bit for the page is turned off and the circular list pointer is advanced." (A Paging Experiment with the Multics System, FJ Corbato, 1968) Change-Id: I0d07e56aa16c67dd36e0d490c3f457f91e46f320 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20882 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-12mem-cache: Fixed a bug in MRU replacement policyMingyuan
The lastTouchTick is set to 0 when instantiate. This will cause the candidate[0] to get evicted over and over again in MRU replacement policy. To resolve this, break the search loop whenever it finds a cold cache line. Change-Id: I33aa57ebe0efca15986f62c3ae10a146bd2b779f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20881 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2019-10-11mem-ruby: Allow Ruby to use all replacement policies in ClassicJingQuJQ
Add support in Ruby to use all replacement policies in Classic. Furthermore, if new replacement policies are added to the Classic system, the Ruby system will recognize new policies without any other changes in Ruby system. The following list all the major changes: * Make Ruby cache entries (AbstractCacheEntry) inherit from Classic cache entries (ReplaceableEntry). By doing this, replacement policies can use cache entries from Ruby caches. AccessPermission and print function are moved from AbstractEntry to AbstractCacheEntry, so AbstractEntry is no longer needed. * DirectoryMemory and all SLICC files are changed to use AbstractCacheEntry as their cache entry interface. So do the python files in mem/slicc/ast which check the entry interface. * "main='false'" argument is added to the protocol files where the DirectoryEntry is defined. This change helps differentiate DirectoryEntry from CacheEntry because they are both the instances of AbstractCacheEntry now. * Use BaseReplacementPolicy in Ruby caches instead of AbstractReplacementPolicy so that Ruby caches will recognize the replacement policies from Classic. * Add getLastAccess() and useOccupancy() function to Classic system so that Ruby caches can use them. Move lastTouchTick to ReplacementData struct because it's needed by getLastAccess() to return the correct value. * Add a 2-dimensional array of ReplacementData in Ruby caches to store information for different replacement policies. Note that, unlike Classic caches, where policy information is stored in cache entries, the policy information needs to be stored in a new 2-dimensional array. This is due to Ruby caches deleting the cache entry every time the corresponding cache line get evicted. Change-Id: Idff6fdd2102a552c103e9d5f31f779aae052943f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20879 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-03mem: Remove unused variableTommaso Marinelli
The variable *sys in dram_ctrl.cc was only used in an assert() check, therefore it has been removed to allow building gem5.fast without errors. A typo in a comment in abstract_mem.hh has also been corrected. Change-Id: I2663545449ecfdb5a27c3574b79dd42beb4a49c8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21380 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-10-01mem-cache: Fix invalid whenReadyDaniel R. Carvalho
When a writeback needs to be allocated the whenReady field of the block is not set, and therefore its access latency calculation uses the previously invalidated value (MaxTick), significantly delaying execution. This is fixed by assuming that the data write portion of a write access is done regardless of previous writes, and that only the tag latency is important for the critical path latency calculation. Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-30mem-ruby: Remove inexistent functions from UtilDaniel R. Carvalho
Remove forward declaration of inexistent functions from RubySlicc_Util.sm. Change-Id: I548bd75cb570371fbdaccf914c5eb9a7b92313d1 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21086 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Make bitSelect use bits<Addr>Daniel R. Carvalho
There is no need to replicate bits<Addr>' functionality. As a side effect, ADDRESS_WIDTH is no longer used and was removed Change-Id: Ia5679f3976c81f779665d82cb758850092f2a293 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21085 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Fix maskLowOrderBitsDaniel R. Carvalho
The function was wrong when number = 63. Also, use the more reliable src/base/bitfield.hh's mbits when posible. maskLowOrderBits has only been kept because SLICC does not accept a templated function. Change-Id: I8dd680da02ceb9e614e2f9cbf8f1ac52cead8d45 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21084 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove shiftLowOrderBitsDaniel R. Carvalho
There is no need to encapsulate a shift operation. Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove maskHighOrderBitsDaniel R. Carvalho
Function was not being used. If needed, src/base/bitfield.hh's mbits can be used instead: maskHighOrderBits(addr, pos) == mbits<Addr>(addr, 64-pos, 0) Change-Id: I3abd041f8d256ec157ba7502182d8588721c2a05 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21082 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem-ruby: Remove bitRemoveDaniel R. Carvalho
bitRemove is not being used anywhere. If needed, can be used as src/base/bitfield.hh's bits: bitRemove(addr, small, big) == ((bits<Addr>(addr, 63, big + 1) << small) | bits<Addr>(addr, small, 0)) Change-Id: I45fd3bc0271ccb659d6a94e3dd00ca095dfd6aa7 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21081 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem: Use new-style stats in the XBar modelsAndreas Sandberg
Migrate to new-world stats with an explicit hierarchy in all of the XBar models. Change-Id: I18b6746a1303ca415638e6d382fb4757607f1123 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21141 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-30mem-cache: Switch to new-style statsAndreas Sandberg
This change puts cache and tag stats into a Stats::Group struct. This makes it easier to identify stat updates (they are prefixed with stat.) and adds hierarchy information for output formats that need it. Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-30mem: Convert DRAM controller to new-style statsAndreas Sandberg
Note that this changes the stat format used by the DRAM controller. Previously, it would have a structure looking a bit like this: - system - dram: Main DRAM controller - dram_0: Rank 0 - dram_1: Rank 1 This structure can't be replicated with new-world stats since stats are confined to the SimObject name space. This means that the new structure looks like this: - system - dram: Main DRAM controller - rank0: Rank 0 - rank1: Rank 1 Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
2019-09-28ruby: 2x protocols has typo/syntax error that fails buildingTimothy Hayes
MOESI_hammer and MOESI_CMP_token contain incorrect lines. Change-Id: I1f9ac429d0f4dcb0241f21c8c9b831bee7aa37a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21259 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-25mem-ruby: prevent cacheProbe being called multiple timesJing Qu
The cacheProbe() function will return the victim entry, and it gets called for multiple times in trigger function in a single miss. This will cause a problem when we try to add a new replacement policy to the Ruby system. Certain policy, like RRIP, will modify the block information every time the getVictim() function gets called. To prevent future problems, we need to store the victim entry, so that we only call it once in one miss. Change-Id: Ic5ca05f789d9bbfb963b8e993ef707020f243702 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21099 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-12 21:00:48 +0000